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ice: implement and use rd32_poll_timeout for ice_sq_done timeout
The ice_sq_done function is used to check the control queue head register and determine whether or not the control queue processing is done. This function is called in a loop checking against jiffies for a specified timeout. The pattern of reading a register in a loop until a condition is true or a timeout is reached is a relatively common pattern. In fact, the kernel provides a read_poll_timeout function implementing this behavior in <linux/iopoll.h> Use of read_poll_timeout is preferred over directly coding these loops. However, using it in the ice driver is a bit more difficult because of the rd32 wrapper. Implement a rd32_poll_timeout wrapper based on read_poll_timeout. Refactor ice_sq_done to use rd32_poll_timeout, replacing the loop calling ice_sq_done in ice_sq_send_cmd. This simplifies the logic down to a single ice_sq_done() call. The implementation of rd32_poll_timeout uses microseconds for its timeout value, so update the CQ timeout macros used to be specified in microseconds units as well instead of using HZ for jiffies. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
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@ -933,19 +933,29 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)
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}
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}
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/**
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/**
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* ice_sq_done - check if FW has processed the Admin Send Queue (ATQ)
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* ice_sq_done - poll until the last send on a control queue has completed
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* @hw: pointer to the HW struct
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* @hw: pointer to the HW struct
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* @cq: pointer to the specific Control queue
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* @cq: pointer to the specific Control queue
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*
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*
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* Returns true if the firmware has processed all descriptors on the
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* Use read_poll_timeout to poll the control queue head, checking until it
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* admin send queue. Returns false if there are still requests pending.
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* matches next_to_use. According to the control queue designers, this has
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* better timing reliability than the DD bit.
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*
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* Return: true if all the descriptors on the send side of a control queue
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* are finished processing, false otherwise.
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*/
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*/
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static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
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static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
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{
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{
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/* AQ designers suggest use of head for better
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u32 head;
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* timing reliability than DD bit
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/* Wait a short time before the initial check, to allow hardware time
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* for completion.
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*/
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*/
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return rd32(hw, cq->sq.head) == cq->sq.next_to_use;
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udelay(5);
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return !rd32_poll_timeout(hw, cq->sq.head,
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head, head == cq->sq.next_to_use,
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20, ICE_CTL_Q_SQ_CMD_TIMEOUT);
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}
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}
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/**
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/**
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@ -969,7 +979,6 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
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struct ice_aq_desc *desc_on_ring;
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struct ice_aq_desc *desc_on_ring;
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bool cmd_completed = false;
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bool cmd_completed = false;
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struct ice_sq_cd *details;
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struct ice_sq_cd *details;
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unsigned long timeout;
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int status = 0;
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int status = 0;
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u16 retval = 0;
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u16 retval = 0;
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u32 val = 0;
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u32 val = 0;
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@ -1063,20 +1072,9 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
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wr32(hw, cq->sq.tail, cq->sq.next_to_use);
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wr32(hw, cq->sq.tail, cq->sq.next_to_use);
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ice_flush(hw);
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ice_flush(hw);
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/* Wait a short time before initial ice_sq_done() check, to allow
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/* Wait for the command to complete. If it finishes within the
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* hardware time for completion.
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* timeout, copy the descriptor back to temp.
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*/
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*/
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udelay(5);
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timeout = jiffies + ICE_CTL_Q_SQ_CMD_TIMEOUT;
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do {
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if (ice_sq_done(hw, cq))
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break;
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usleep_range(100, 150);
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} while (time_before(jiffies, timeout));
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/* if ready, copy the desc back to temp */
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if (ice_sq_done(hw, cq)) {
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if (ice_sq_done(hw, cq)) {
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memcpy(desc, desc_on_ring, sizeof(*desc));
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memcpy(desc, desc_on_ring, sizeof(*desc));
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if (buf) {
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if (buf) {
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@ -43,7 +43,7 @@ enum ice_ctl_q {
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};
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};
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/* Control Queue timeout settings - max delay 1s */
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/* Control Queue timeout settings - max delay 1s */
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#define ICE_CTL_Q_SQ_CMD_TIMEOUT HZ /* Wait max 1s */
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#define ICE_CTL_Q_SQ_CMD_TIMEOUT USEC_PER_SEC
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#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */
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#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */
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#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */
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#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */
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@ -12,6 +12,7 @@
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#include <linux/ethtool.h>
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#include <linux/ethtool.h>
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#include <linux/etherdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/if_ether.h>
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#include <linux/if_ether.h>
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#include <linux/iopoll.h>
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#include <linux/pci_ids.h>
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#include <linux/pci_ids.h>
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#ifndef CONFIG_64BIT
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#ifndef CONFIG_64BIT
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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@ -23,6 +24,9 @@
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#define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
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#define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
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#define rd64(a, reg) readq((a)->hw_addr + (reg))
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#define rd64(a, reg) readq((a)->hw_addr + (reg))
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#define rd32_poll_timeout(a, addr, val, cond, delay_us, timeout_us) \
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read_poll_timeout(rd32, val, cond, delay_us, timeout_us, false, a, addr)
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#define ice_flush(a) rd32((a), GLGEN_STAT)
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#define ice_flush(a) rd32((a), GLGEN_STAT)
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#define ICE_M(m, s) ((m ## U) << (s))
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#define ICE_M(m, s) ((m ## U) << (s))
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