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The ice_sq_done function is used to check the control queue head register and determine whether or not the control queue processing is done. This function is called in a loop checking against jiffies for a specified timeout. The pattern of reading a register in a loop until a condition is true or a timeout is reached is a relatively common pattern. In fact, the kernel provides a read_poll_timeout function implementing this behavior in <linux/iopoll.h> Use of read_poll_timeout is preferred over directly coding these loops. However, using it in the ice driver is a bit more difficult because of the rd32 wrapper. Implement a rd32_poll_timeout wrapper based on read_poll_timeout. Refactor ice_sq_done to use rd32_poll_timeout, replacing the loop calling ice_sq_done in ice_sq_send_cmd. This simplifies the logic down to a single ice_sq_done() call. The implementation of rd32_poll_timeout uses microseconds for its timeout value, so update the CQ timeout macros used to be specified in microseconds units as well instead of using HZ for jiffies. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
108 lines
2.8 KiB
C
108 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_CONTROLQ_H_
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#define _ICE_CONTROLQ_H_
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#include "ice_adminq_cmd.h"
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/* Maximum buffer lengths for all control queue types */
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#define ICE_AQ_MAX_BUF_LEN 4096
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#define ICE_MBXQ_MAX_BUF_LEN 4096
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#define ICE_SBQ_MAX_BUF_LEN 512
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#define ICE_CTL_Q_DESC(R, i) \
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(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
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#define ICE_CTL_Q_DESC_UNUSED(R) \
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((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
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(R)->next_to_clean - (R)->next_to_use - 1))
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/* Defines that help manage the driver vs FW API checks.
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* Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
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*/
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#define EXP_FW_API_VER_MAJOR_E810 0x01
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#define EXP_FW_API_VER_MINOR_E810 0x05
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#define EXP_FW_API_VER_MAJOR_E830 0x01
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#define EXP_FW_API_VER_MINOR_E830 0x07
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#define EXP_FW_API_VER_MAJOR_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \
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EXP_FW_API_VER_MAJOR_E830 : \
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EXP_FW_API_VER_MAJOR_E810)
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#define EXP_FW_API_VER_MINOR_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \
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EXP_FW_API_VER_MINOR_E830 : \
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EXP_FW_API_VER_MINOR_E810)
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/* Different control queue types: These are mainly for SW consumption. */
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enum ice_ctl_q {
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ICE_CTL_Q_UNKNOWN = 0,
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ICE_CTL_Q_ADMIN,
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ICE_CTL_Q_MAILBOX,
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ICE_CTL_Q_SB,
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};
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/* Control Queue timeout settings - max delay 1s */
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#define ICE_CTL_Q_SQ_CMD_TIMEOUT USEC_PER_SEC
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#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */
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#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */
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struct ice_ctl_q_ring {
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void *dma_head; /* Virtual address to DMA head */
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struct ice_dma_mem desc_buf; /* descriptor ring memory */
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void *cmd_buf; /* command buffer memory */
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union {
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struct ice_dma_mem *sq_bi;
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struct ice_dma_mem *rq_bi;
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} r;
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u16 count; /* Number of descriptors */
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/* used for interrupt processing */
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u16 next_to_use;
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u16 next_to_clean;
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/* used for queue tracking */
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u32 head;
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u32 tail;
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u32 len;
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u32 bah;
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u32 bal;
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u32 len_mask;
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u32 len_ena_mask;
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u32 len_crit_mask;
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u32 head_mask;
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};
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/* sq transaction details */
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struct ice_sq_cd {
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struct ice_aq_desc *wb_desc;
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};
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#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
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/* rq event information */
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struct ice_rq_event_info {
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struct ice_aq_desc desc;
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u16 msg_len;
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u16 buf_len;
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u8 *msg_buf;
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};
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/* Control Queue information */
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struct ice_ctl_q_info {
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enum ice_ctl_q qtype;
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struct ice_ctl_q_ring rq; /* receive queue */
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struct ice_ctl_q_ring sq; /* send queue */
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u16 num_rq_entries; /* receive queue depth */
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u16 num_sq_entries; /* send queue depth */
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u16 rq_buf_size; /* receive queue buffer size */
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u16 sq_buf_size; /* send queue buffer size */
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enum ice_aq_err sq_last_status; /* last status on send queue */
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struct mutex sq_lock; /* Send queue lock */
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struct mutex rq_lock; /* Receive queue lock */
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};
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#endif /* _ICE_CONTROLQ_H_ */
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