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Merge tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

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Pull sophgo SoC devicetree updates from Arnd Bergmann:
 "The Sophgo SG2044 SoC is their second generation server chip with 64
  cores, following the SG2042.

  In addition, there are minor updates for the cv180x SoCs"

* tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX
  riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
  dt-bindings: riscv: sophgo: Add SG2044 compatible string
  dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC
  dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi
  riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
  riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
  riscv: dts: sophgo: Move riscv cpu definition to a separate file
  riscv: dts: sophgo: Move all soc specific device into soc dtsi file
  riscv: sophgo: dts: Add spi controller for SG2042
  riscv: dts: sophgo: sg2042: add pinctrl support
This commit is contained in:
Linus Torvalds
2025-05-31 08:14:37 -07:00
parent ec71f661a5 9bba618694
commit 31848987f1
16 changed files with 3508 additions and 113 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View File

@@ -70,6 +70,7 @@ properties:
- sophgo,cv1812h-plic
- sophgo,sg2002-plic
- sophgo,sg2042-plic
- sophgo,sg2044-plic
- thead,th1520-plic
- const: thead,c900-plic
- items:

1
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
View File

@@ -14,6 +14,7 @@ properties:
items:
- enum:
- sophgo,sg2042-aclint-mswi
- sophgo,sg2044-aclint-mswi
- const: thead,c900-aclint-mswi
reg:

4
Documentation/devicetree/bindings/riscv/sophgo.yaml
View File

@@ -35,6 +35,10 @@ properties:
- enum:
- milkv,pioneer
- const: sophgo,sg2042
- items:
- enum:
- sophgo,srd3-10
- const: sophgo,sg2044
additionalProperties: true

1
arch/riscv/boot/dts/sophgo/Makefile
View File

@@ -3,3 +3,4 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb

43
arch/riscv/boot/dts/sophgo/cv1800b.dtsi
View File

@@ -3,8 +3,11 @@
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
#include "cv18xx.dtsi"
#include "cv180x-cpus.dtsi"
#include "cv180x.dtsi"
/ {
compatible = "sophgo,cv1800b";
@@ -15,23 +18,37 @@
};
soc {
interrupt-parent = <&plic>;
dma-noncoherent;
pinctrl: pinctrl@3001000 {
compatible = "sophgo,cv1800b-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
clk: clock-controller@3002000 {
compatible = "sophgo,cv1800b-clk";
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
plic: interrupt-controller@70000000 {
compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};
&plic {
compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
};
&clint {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};
&clk {
compatible = "sophgo,cv1800-clk";
};

36
arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi Normal file
View File

@@ -0,0 +1,36 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
/ {
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
};

95
arch/riscv/boot/dts/sophgo/cv18xx.dtsi → arch/riscv/boot/dts/sophgo/cv180x.dtsi
View File

@@ -12,35 +12,6 @@
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";
@@ -49,18 +20,10 @@
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <1>;
#size-cells = <1>;
dma-noncoherent;
ranges;
clk: clock-controller@3002000 {
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
gpio0: gpio@3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;
@@ -75,7 +38,7 @@
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -93,7 +56,7 @@
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -111,7 +74,7 @@
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -129,7 +92,7 @@
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -137,7 +100,7 @@
compatible = "sophgo,cv1800b-saradc";
reg = <0x030f0000 0x1000>;
clocks = <&clk CLK_SARADC>;
interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -162,7 +125,7 @@
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
clock-names = "ref", "pclk";
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -173,7 +136,7 @@
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
clock-names = "ref", "pclk";
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -184,7 +147,7 @@
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
clock-names = "ref", "pclk";
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -195,7 +158,7 @@
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
clock-names = "ref", "pclk";
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -206,14 +169,14 @@
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
clock-names = "ref", "pclk";
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
@@ -224,7 +187,7 @@
uart1: serial@4150000 {
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
@@ -235,7 +198,7 @@
uart2: serial@4160000 {
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
@@ -246,7 +209,7 @@
uart3: serial@4170000 {
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
@@ -261,7 +224,7 @@
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
clock-names = "ssi_clk", "pclk";
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -272,7 +235,7 @@
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
clock-names = "ssi_clk", "pclk";
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -283,7 +246,7 @@
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
clock-names = "ssi_clk", "pclk";
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -294,14 +257,14 @@
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
clock-names = "ssi_clk", "pclk";
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
@@ -312,7 +275,7 @@
sdhci0: mmc@4310000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4310000 0x1000>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_SD0>,
<&clk CLK_SD0>;
clock-names = "core", "bus";
@@ -322,7 +285,7 @@
sdhci1: mmc@4320000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4320000 0x1000>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_SD1>,
<&clk CLK_SD1>;
clock-names = "core", "bus";
@@ -332,7 +295,7 @@
dmac: dma-controller@4330000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x04330000 0x1000>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
@@ -344,19 +307,5 @@
snps,data-width = <2>;
status = "disabled";
};
plic: interrupt-controller@70000000 {
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};

43
arch/riscv/boot/dts/sophgo/cv1812h.dtsi
View File

@@ -3,9 +3,12 @@
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
#include "cv18xx.dtsi"
#include "cv180x-cpus.dtsi"
#include "cv180x.dtsi"
#include "cv181x.dtsi"
/ {
@@ -17,23 +20,37 @@
};
soc {
interrupt-parent = <&plic>;
dma-noncoherent;
pinctrl: pinctrl@3001000 {
compatible = "sophgo,cv1812h-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
clk: clock-controller@3002000 {
compatible = "sophgo,cv1812h-clk";
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
plic: interrupt-controller@70000000 {
compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};
&plic {
compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
};
&clint {
compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
};
&clk {
compatible = "sophgo,cv1810-clk";
};

2
arch/riscv/boot/dts/sophgo/cv181x.dtsi
View File

@@ -11,7 +11,7 @@
emmc: mmc@4300000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4300000 0x1000>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_EMMC>,
<&clk CLK_EMMC>;
clock-names = "core", "bus";

43
arch/riscv/boot/dts/sophgo/sg2002.dtsi
View File

@@ -3,9 +3,12 @@
* Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
*/
#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-sg2002.h>
#include "cv18xx.dtsi"
#include "cv180x-cpus.dtsi"
#include "cv180x.dtsi"
#include "cv181x.dtsi"
/ {
@@ -17,27 +20,41 @@
};
soc {
interrupt-parent = <&plic>;
dma-noncoherent;
pinctrl: pinctrl@3001000 {
compatible = "sophgo,sg2002-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
clk: clock-controller@3002000 {
compatible = "sophgo,sg2002-clk", "sophgo,sg2000-clk";
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
plic: interrupt-controller@70000000 {
compatible = "sophgo,sg2002-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
compatible = "sophgo,sg2002-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};
&plic {
compatible = "sophgo,sg2002-plic", "thead,c900-plic";
};
&clint {
compatible = "sophgo,sg2002-clint", "thead,c900-clint";
};
&clk {
compatible = "sophgo,sg2000-clk";
};
&sdhci0 {
compatible = "sophgo,sg2002-dwcmshc";
};

72
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
View File

@@ -42,6 +42,8 @@
};
&emmc {
pinctrl-0 = <&emmc_cfg>;
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
no-sd;
@@ -51,6 +53,8 @@
};
&i2c1 {
pinctrl-0 = <&i2c1_cfg>;
pinctrl-names = "default";
status = "okay";
mcu: syscon@17 {
@@ -60,7 +64,73 @@
};
};
&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
sdhci-emmc-cd-pins {
pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
sdhci-emmc-rst-pwr-pins {
pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
<PINMUX(PIN_EMMC_PWR_EN, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
};
i2c1_cfg: i2c1-cfg {
i2c1-pins {
pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
<PINMUX(PIN_IIC1_SCL, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
sd_cfg: sdhci-sd-cfg {
sdhci-sd-cd-wp-pins {
pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
<PINMUX(PIN_SDIO_WP, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
sdhci-sd-rst-pwr-pins {
pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
<PINMUX(PIN_SDIO_PWR_EN, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
};
uart0_cfg: uart0-cfg {
uart0-rx-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
};
&sd {
pinctrl-0 = <&sd_cfg>;
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
no-mmc;
@@ -69,6 +139,8 @@
};
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
status = "okay";
};

32
arch/riscv/boot/dts/sophgo/sg2042.dtsi
View File

@@ -8,6 +8,7 @@
#include <dt-bindings/clock/sophgo,sg2042-pll.h>
#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-sg2042.h>
#include <dt-bindings/reset/sophgo,sg2042-reset.h>
#include "sg2042-cpus.dtsi"
@@ -200,6 +201,11 @@
#clock-cells = <1>;
};
pinctrl: pinctrl@7030011000 {
compatible = "sophgo,sg2042-pinctrl";
reg = <0x70 0x30011000 0x0 0x1000>;
};
clkgen: clock-controller@7030012000 {
compatible = "sophgo,sg2042-clkgen";
reg = <0x70 0x30012000 0x0 0x1000>;
@@ -537,6 +543,32 @@
status = "disabled";
};
spi0: spi@7040004000 {
compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
reg = <0x70 0x40004000 0x00 0x1000>;
clocks = <&clkgen GATE_CLK_APB_SPI>;
interrupt-parent = <&intc>;
interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
num-cs = <2>;
resets = <&rstgen RST_SPI0>;
status = "disabled";
};
spi1: spi@7040005000 {
compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
reg = <0x70 0x40005000 0x00 0x1000>;
clocks = <&clkgen GATE_CLK_APB_SPI>;
interrupt-parent = <&intc>;
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
num-cs = <2>;
resets = <&rstgen RST_SPI1>;
status = "disabled";
};
emmc: mmc@704002a000 {
compatible = "sophgo,sg2042-dwcmshc";
reg = <0x70 0x4002a000 0x0 0x1000>;

3002
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi Normal file
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128
arch/riscv/boot/dts/sophgo/sg2044-reset.h Normal file
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@@ -0,0 +1,128 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
*/
#ifndef _SG2044_RESET_H
#define _SG2044_RESET_H
#define RST_AP_SYS 0
#define RST_AP_SYS_CORE0 1
#define RST_AP_SYS_CORE1 2
#define RST_AP_SYS_CORE2 3
#define RST_AP_SYS_CORE3 4
#define RST_AP_PIC 5
#define RST_AP_TDT 6
#define RST_RP_PIC_TDT 7
#define RST_HSDMA 8
#define RST_SYSDMA 9
#define RST_EFUSE0 10
#define RST_EFUSE1 11
#define RST_RTC 12
#define RST_TIMER 13
#define RST_WDT 14
#define RST_AHB_ROM0 15
#define RST_AHB_ROM1 16
#define RST_I2C0 17
#define RST_I2C1 18
#define RST_I2C2 19
#define RST_I2C3 20
#define RST_GPIO0 21
#define RST_GPIO1 22
#define RST_GPIO2 23
#define RST_PWM 24
#define RST_AXI_SRAM0 25
#define RST_AXI_SRAM1 26
#define RST_SPIFMC0 27
#define RST_SPIFMC1 28
#define RST_MAILBOX 29
#define RST_ETH0 30
#define RST_EMMC 31
#define RST_SD 32
#define RST_UART0 33
#define RST_UART1 34
#define RST_UART2 35
#define RST_UART3 36
#define RST_SPI0 37
#define RST_SPI1 38
#define RST_MTLI 39
#define RST_DBG_I2C 40
#define RST_C2C0 41
#define RST_C2C1 42
#define RST_C2C2 43
#define RST_C2C3 44
#define RST_CXP 45
#define RST_DDR0 46
#define RST_DDR1 47
#define RST_DDR2 48
#define RST_DDR3 49
#define RST_DDR4 50
#define RST_DDR5 51
#define RST_DDR6 52
#define RST_DDR7 53
#define RST_DDR8 54
#define RST_DDR9 55
#define RST_DDR10 56
#define RST_DDR11 57
#define RST_DDR12 58
#define RST_DDR13 59
#define RST_DDR14 60
#define RST_DDR15 61
#define RST_BAR 62
#define RST_K2K 63
#define RST_CC_SYS_X1Y1 64
#define RST_CC_SYS_X1Y2 65
#define RST_CC_SYS_X1Y3 66
#define RST_CC_SYS_X1Y4 67
#define RST_CC_SYS_X0Y1 68
#define RST_CC_SYS_X0Y2 69
#define RST_CC_SYS_X0Y3 70
#define RST_CC_SYS_X0Y4 71
#define RST_SC_X1Y1 80
#define RST_SC_X1Y2 81
#define RST_SC_X1Y3 82
#define RST_SC_X1Y4 83
#define RST_SC_X0Y1 84
#define RST_SC_X0Y2 85
#define RST_SC_X0Y3 86
#define RST_SC_X0Y4 87
#define RST_RP_CLUSTER_X1Y1_S0 160
#define RST_RP_CLUSTER_X1Y1_S1 161
#define RST_RP_CLUSTER_X1Y2_S0 162
#define RST_RP_CLUSTER_X1Y2_S1 163
#define RST_RP_CLUSTER_X1Y3_S0 164
#define RST_RP_CLUSTER_X1Y3_S1 165
#define RST_RP_CLUSTER_X1Y4_S0 166
#define RST_RP_CLUSTER_X1Y4_S1 167
#define RST_RP_CLUSTER_X0Y1_W0 168
#define RST_RP_CLUSTER_X0Y1_W1 169
#define RST_RP_CLUSTER_X0Y2_W0 170
#define RST_RP_CLUSTER_X0Y2_W1 171
#define RST_RP_CLUSTER_X0Y3_W0 172
#define RST_RP_CLUSTER_X0Y3_W1 173
#define RST_RP_CLUSTER_X0Y4_W0 174
#define RST_RP_CLUSTER_X0Y4_W1 175
#define RST_TPSYS_X1Y1 180
#define RST_TPSYS_X1Y2 181
#define RST_TPSYS_X1Y3 182
#define RST_TPSYS_X1Y4 183
#define RST_TPSYS_X0Y1 184
#define RST_TPSYS_X0Y2 185
#define RST_TPSYS_X0Y3 186
#define RST_TPSYS_X0Y4 187
#define RST_SPACC 188
#define RST_PKA 189
#define RST_SE_TRNG 190
#define RST_SE_DBG 191
#define RST_SE_FAB_FW 192
#define RST_SE_CTRL 193
#define RST_MAILBOX0 194
#define RST_MAILBOX1 195
#define RST_MAILBOX2 196
#define RST_MAILBOX3 197
#define RST_INTC0 198
#define RST_INTC1 199
#define RST_INTC2 200
#define RST_INTC3 201
#endif /* _DT_BINDINGS_SG2044_RESET_H */

32
arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts Normal file
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@@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
*/
/dts-v1/;
#include "sg2044.dtsi"
/ {
model = "Sophgo SG2044 SRD3-10";
compatible = "sophgo,srd3-10", "sophgo,sg2044";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
};
chosen {
stdout-path = "serial1:115200n8";
};
};
&osc {
clock-frequency = <25000000>;
};
&uart1 {
status = "okay";
};

86
arch/riscv/boot/dts/sophgo/sg2044.dtsi Normal file
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@@ -0,0 +1,86 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "sg2044-cpus.dtsi"
#include "sg2044-reset.h"
/ {
compatible = "sophgo,sg2044";
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000010 0x00000000>;
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
uart0: serial@7030000000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30000000 0x0 0x1000>;
clock-frequency = <500000000>;
interrupt-parent = <&intc>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART0>;
status = "disabled";
};
uart1: serial@7030001000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30001000 0x0 0x1000>;
clock-frequency = <500000000>;
interrupt-parent = <&intc>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART1>;
status = "disabled";
};
uart2: serial@7030002000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30002000 0x0 0x1000>;
clock-frequency = <500000000>;
interrupt-parent = <&intc>;
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART2>;
status = "disabled";
};
uart3: serial@7030003000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30003000 0x0 0x1000>;
clock-frequency = <500000000>;
interrupt-parent = <&intc>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART3>;
status = "disabled";
};
rst: reset-controller@7050003000 {
compatible = "sophgo,sg2044-reset",
"sophgo,sg2042-reset";
reg = <0x70 0x50003000 0x0 0x1000>;
#reset-cells = <1>;
};
};
};