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As sg2000 and sg2002 can boot from an arm a53 core, it is not suitable to left the riscv cpu definition in the common peripheral header. Move the riscv related device into a separate header file, so the arm subsystem can reuse the common peripheral header. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250430012654.235830-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
37 lines
865 B
Plaintext
37 lines
865 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
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*/
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/ {
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <25000000>;
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cpu0: cpu@0 {
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compatible = "thead,c906", "riscv";
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device_type = "cpu";
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reg = <0>;
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d-cache-block-size = <64>;
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d-cache-sets = <512>;
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d-cache-size = <65536>;
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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mmu-type = "riscv,sv39";
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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};
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};
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