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cfd9d70a855edf6adb37d0ed88be9e35274dbe49
linux/arch/arc/include/asm
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Vineet Gupta cfd9d70a85 ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg 
ARC700 exception (and intr handling) didn't have auto stack switching
thus had to rely on stashing a reg temporarily (to free it up) at a
known place in memory, allowing to code up the low level stack switching.
This however was not re-entrant in SMP which thus had to repurpose the
per-cpu MMU SCRATCH DATA register otherwise used to "cache" the task pdg
pointer (vs. reading it from mm struct)

The newer HS cores do have auto-stack switching and thus even SMP builds
can use the MMU SCRATCH reg as originally intended.

This patch fixes the restriction to ARC700 SMP builds only

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-10-28 12:12:31 -07:00
..
arcregs.h
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asm-offsets.h
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atomic.h
Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
2019-07-08 16:12:03 -07:00
barrier.h
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bitops.h
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bug.h
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cache.h
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cacheflush.h
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checksum.h
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cmpxchg.h
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current.h
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delay.h
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disasm.h
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dma.h
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dwarf.h
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elf.h
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entry-arcv2.h
ARCv2: entry: early return from exception need not clear U & DE bits
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entry-compact.h
ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg
2019-10-28 12:12:31 -07:00
entry.h
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exec.h
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fb.h
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
2017-11-02 11:10:55 +01:00
futex.h
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highmem.h
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hugepage.h
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io.h
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irq.h
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irqflags-arcv2.h
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irqflags-compact.h
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irqflags.h
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Kbuild
arch: Use asm-generic header for asm/mmiowb.h
2019-04-08 11:59:43 +01:00
kdebug.h
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kgdb.h
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kmap_types.h
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kprobes.h
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linkage.h
arc: prefer __section from compiler_attributes.h
2019-08-26 22:37:12 +05:30
mach_desc.h
arc: prefer __section from compiler_attributes.h
2019-08-26 22:37:12 +05:30
mmu_context.h
ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg
2019-10-28 12:12:31 -07:00
mmu.h
ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg
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mmzone.h
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module.h
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page.h
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pci.h
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perf_event.h
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pgalloc.h
mm: treewide: clarify pgtable_page_{ctor,dtor}() naming
2019-09-26 10:10:44 -07:00
pgtable.h
ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg
2019-10-28 12:12:31 -07:00
processor.h
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ptrace.h
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sections.h
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segment.h
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serial.h
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setup.h
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shmparam.h
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smp.h
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spinlock_types.h
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spinlock.h
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stacktrace.h
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string.h
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switch_to.h
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syscall.h
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syscalls.h
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thread_info.h
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timex.h
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tlb-mmu1.h
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tlb.h
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tlbflush.h
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uaccess.h
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unaligned.h
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unwind.h
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