Vineet Gupta cfd9d70a85 ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg ...

ARC700 exception (and intr handling) didn't have auto stack switching
thus had to rely on stashing a reg temporarily (to free it up) at a
known place in memory, allowing to code up the low level stack switching.
This however was not re-entrant in SMP which thus had to repurpose the
per-cpu MMU SCRATCH DATA register otherwise used to "cache" the task pdg
pointer (vs. reading it from mm struct)

The newer HS cores do have auto-stack switching and thus even SMP builds
can use the MMU SCRATCH reg as originally intended.

This patch fixes the restriction to ARC700 SMP builds only

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

2019-10-28 12:12:31 -07:00

..

asm

ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg

2019-10-28 12:12:31 -07:00

uapi/asm

treewide: Add SPDX license identifier - Kbuild

2019-05-30 11:32:33 -07:00