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linux/Documentation
Hyungwon Hwang 26269af95a drm/exynos: dsi: rename pll_clk to sclk_clk
This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk
is actually not the pll input clock for dsi. The pll input clock comes
from the board's oscillator directly. But for the backward
compatibility, the old clock name "pll_clk" is also OK.

Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-22 20:05:00 +09:00
..
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2015-05-10 19:26:37 +02:00
2015-05-11 17:17:50 +02:00
2014-06-19 17:45:14 -07:00
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2014-12-08 09:07:11 -05:00
2014-11-21 19:48:50 +05:30
2014-09-23 23:44:16 -07:00