Stephen Boyd
ee2d2a4e9c
Merge branches 'clk-aspeed', 'clk-keystone', 'clk-mobileye' and 'clk-allwinner' into clk-next
...
* clk-aspeed:
clk: ast2600: Add FSI parent clock with correct rate
dt-bindings: clock: ast2600: Add FSI clock
* clk-keystone:
clk: keystone: sci-clk: Adding support for non contiguous clocks
* clk-mobileye:
dt-bindings: reset: mobileye,eyeq5-reset: add bindings
dt-bindings: clock: mobileye,eyeq5-clk: add bindings
clk: fixed-factor: add fwname-based constructor functions
clk: fixed-factor: add optional accuracy support
* clk-allwinner:
clk: sunxi: usb: fix kernel-doc warnings
clk: sunxi: sun9i-cpus: fix kernel-doc warnings
clk: sunxi: a20-gmac: fix kernel-doc warnings
2024-03-13 12:34:04 -07:00
Stephen Boyd
cf5f06c8ee
Merge branches 'clk-renesas', 'clk-cleanup', 'clk-hisilicon', 'clk-mediatek' and 'clk-bulk' into clk-next
...
- Add a devm_clk_bulk_get_all_enable() API to get and enable all clks
for a device
- Fix some static checker errors in the hisilicon clk driver
* clk-renesas: (25 commits)
clk: renesas: r8a779h0: Add RPC-IF clock
clk: renesas: r8a779h0: Add SYS-DMAC clocks
clk: renesas: r8a779h0: Add SDHI clock
clk: renesas: r8a779h0: Add EtherAVB clocks
clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
clk: renesas: r8a779h0: Add I2C clocks
clk: renesas: r8a779h0: Add watchdog clock
clk: renesas: r8a779h0: Add PFC/GPIO clocks
clk: renesas: r8a779g0: Fix PCIe clock name
clk: renesas: cpg-mssr: Add support for R-Car V4M
clk: renesas: rcar-gen4: Add support for FRQCRC1
clk: renesas: r9a07g043: Add clock and reset entries for CRU
clk: renesas: r9a08g045: Add clock and reset support for watchdog
dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support
dt-bindings: power: Add r8a779h0 SYSC power domain definitions
dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support
...
* clk-cleanup:
clk: zynq: Prevent null pointer dereference caused by kmalloc failure
clk: fractional-divider: Use bit operations consistently
clk: fractional-divider: Move mask calculations out of lock
clk: ti: dpll3xxx: use correct function names in kernel-doc
clk: clocking-wizard: Remove redundant initialization of pointer div_addr
clk: keystone: sci-clk: match func name comment to actual
clk: cdce925: Remove redundant assignment to variable 'rate'
MAINTAINERS: drop Sekhar Nori
* clk-hisilicon:
clk: hisilicon: Use devm_kcalloc() instead of devm_kzalloc()
clk: hisilicon: hi3559a: Fix an erroneous devm_kfree()
clk: hisilicon: hi3519: Release the correct number of gates in hi3519_clk_unregister()
* clk-mediatek:
clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe()
clk: mediatek: add infracfg reset controller for mt7988
dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs
dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clock
dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock
dt-bindings: clock: mediatek: convert hifsys to the json-schema clock
clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF
clk: mediatek: mt7622-apmixedsys: Fix an error handling path in clk_mt8135_apmixed_probe()
clk: mediatek: mt8135: Fix an error handling path in clk_mt8135_apmixed_probe()
* clk-bulk:
clk: Provide managed helper to get and enable bulk clocks
2024-03-13 12:33:44 -07:00
Duoming Zhou
7938e9ce39
clk: zynq: Prevent null pointer dereference caused by kmalloc failure
...
The kmalloc() in zynq_clk_setup() will return null if the
physical memory has run out. As a result, if we use snprintf()
to write data to the null address, the null pointer dereference
bug will happen.
This patch uses a stack variable to replace the kmalloc().
Fixes: 0ee52b157bmichal.simek@amd.com >
Suggested-by: Stephen Boyd <sboyd@kernel.org >
Signed-off-by: Duoming Zhou <duoming@zju.edu.cn >
Link: https://lore.kernel.org/r/20240301084437.16084-1-duoming@zju.edu.cn
Acked-by: Michal Simek <michal.simek@amd.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-03-08 17:15:20 -08:00
Andy Shevchenko
c1ab111e62
clk: fractional-divider: Use bit operations consistently
...
Use BIT() where makes sense. This alings usage of bit operations
in the same pieces of code. Moreover, strictly speaking by the
letter of the C standard, left shift of 1 by 31 bits is UB (undefined
behaviour), switching to BIT() addresses that as well.
Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com >
Link: https://lore.kernel.org/r/20240303120732.240355-1-andy.shevchenko@gmail.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-03-08 17:07:11 -08:00
Andy Shevchenko
6e3f07f9df
clk: fractional-divider: Move mask calculations out of lock
...
There is no need to calculate masks under the lock taken.
Move them out of it.
Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com >
Link: https://lore.kernel.org/r/20240303121410.240761-1-andy.shevchenko@gmail.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: Heiko Stuebner <heiko@sntech.de >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-03-08 17:04:04 -08:00
Markus Elfring
f40056a5b4
clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe()
...
Add a label so that a bit of exception handling can be better reused
at the end of this function implementation.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net >
Link: https://lore.kernel.org/r/6a64e7b3-b1ce-46c4-9c85-89f731aee592@web.de
Reviewed-by: AngeloGiaocchino Del Regno <angelogioacchino.delregno@collabora.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-28 17:13:53 -08:00
Randy Dunlap
9b6c057bc1
clk: ti: dpll3xxx: use correct function names in kernel-doc
...
Use function names that match the implementation in kernel-doc comments
to avoid kernel-doc warnings:
dpll3xxx.c:938: warning: expecting prototype for omap3_non_core_dpll_save_context(). Prototype was for omap3_noncore_dpll_save_context() instead
dpll3xxx.c:967: warning: expecting prototype for omap3_core_dpll_restore_context(). Prototype was for omap3_noncore_dpll_restore_context() instead
Signed-off-by: Randy Dunlap <rdunlap@infradead.org >
Cc: Tero Kristo <kristo@kernel.org >
Cc: linux-omap@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com >
Cc: Stephen Boyd <sboyd@kernel.org >
Cc: linux-clk@vger.kernel.org
Link: https://lore.kernel.org/r/20240115054739.4988-1-rdunlap@infradead.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-28 15:19:03 -08:00
Colin Ian King
732b1c2c9f
clk: clocking-wizard: Remove redundant initialization of pointer div_addr
...
The pointer div_addr is being assigned a value that is never used, it is
being re-assigned a different value near the end of the function where
it is being read in the next statement. The initialization is redundant
and can be removed.
Cleans up clang scan build warning:
drivers/clk/xilinx/clk-xlnx-clock-wizard.c:501:16: warning: Value stored
to 'div_addr' during its initialization is never read [deadcode.DeadStores]
Signed-off-by: Colin Ian King <colin.i.king@gmail.com >
Link: https://lore.kernel.org/r/20240223134347.3908301-1-colin.i.king@gmail.com
Reviewed-by: Michal Simek <michal.simek@amd.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-28 14:51:51 -08:00
Stephen Boyd
84448fa6e3
Merge tag 'sunxi-clk-for-6.9-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
...
Pull Allwinner clk driver updates from Jernej Skrabec:
- fix kerneldoc warnings
* tag 'sunxi-clk-for-6.9-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux :
clk: sunxi: usb: fix kernel-doc warnings
clk: sunxi: sun9i-cpus: fix kernel-doc warnings
clk: sunxi: a20-gmac: fix kernel-doc warnings
2024-02-27 14:15:28 -08:00
Stephen Boyd
9bd5726ffb
Merge tag 'renesas-clk-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
...
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on
R-Car V4M
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779h0: Add RPC-IF clock
clk: renesas: r8a779h0: Add SYS-DMAC clocks
clk: renesas: r8a779h0: Add SDHI clock
clk: renesas: r8a779h0: Add EtherAVB clocks
clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
2024-02-27 14:13:23 -08:00
Théo Lebrun
c6e0897eca
dt-bindings: reset: mobileye,eyeq5-reset: add bindings
...
Add DT-Schema bindings for the EyeQ5 reset controller.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com >
Link: https://lore.kernel.org/r/20240221-mbly-clk-v7-4-31d4ce3630c3@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 22:14:41 -08:00
Théo Lebrun
4a85e82658
dt-bindings: clock: mobileye,eyeq5-clk: add bindings
...
Add DT schema bindings for the EyeQ5 clock controller driver.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com >
Link: https://lore.kernel.org/r/20240221-mbly-clk-v7-3-31d4ce3630c3@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 22:14:28 -08:00
Théo Lebrun
ae156a3633
clk: fixed-factor: add fwname-based constructor functions
...
Add four functions to register clk_hw based on the fw_name field in
clk_parent_data, ie the value in the DT property `clock-names`.
There are variants for devm or not and passing an accuracy or not
passing one:
- clk_hw_register_fixed_factor_fwname
- clk_hw_register_fixed_factor_with_accuracy_fwname
- devm_clk_hw_register_fixed_factor_fwname
- devm_clk_hw_register_fixed_factor_with_accuracy_fwname
The `struct clk_parent_data` init is extracted from
__clk_hw_register_fixed_factor to each calling function. It is required
to allow each function to pass whatever field they want, not only index.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com >
Link: https://lore.kernel.org/r/20240221-mbly-clk-v7-2-31d4ce3630c3@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 22:11:51 -08:00
Théo Lebrun
ff773fd219
clk: fixed-factor: add optional accuracy support
...
Fixed factor clock reports the parent clock accuracy. Add flags and acc
fields to `struct clk_fixed_factor` to support setting a fixed
accuracy. The default if no flag is set is not changed: use the parent
clock accuracy.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com >
Link: https://lore.kernel.org/r/20240221-mbly-clk-v7-1-31d4ce3630c3@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 22:11:48 -08:00
Udit Kumar
ad3ac13c6e
clk: keystone: sci-clk: Adding support for non contiguous clocks
...
Most of clocks and their parents are defined in contiguous range,
But in few cases, there is gap in clock numbers[0].
Driver assumes clocks to be in contiguous range, and add their clock
ids incrementally.
New firmware started returning error while calling get_freq and is_on
API for non-available clock ids.
In this fix, driver checks and adds only valid clock ids.
[0] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html
Section Clocks for NAVSS0_CPTS_0 Device, clock id 12-15 not present.
Fixes: 3c13933c60u-kumar1@ti.com >
Link: https://lore.kernel.org/r/20240213082640.457316-1-u-kumar1@ti.com
Reviewed-by: Nishanth Menon <nm@ti.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 21:59:48 -08:00
Randy Dunlap
05dbb505db
clk: keystone: sci-clk: match func name comment to actual
...
Correct the function name in the kernel-doc comment to match the
actual function name to avoid a kernel-doc warning:
drivers/clk/keystone/sci-clk.c:287: warning: expecting prototype for _sci_clk_get(). Prototype was for _sci_clk_build() instead
Signed-off-by: Randy Dunlap <rdunlap@infradead.org >
Cc: Nishanth Menon <nm@ti.com >
Cc: Tero Kristo <kristo@kernel.org >
Cc: Santosh Shilimkar <ssantosh@kernel.org >
Cc: linux-arm-kernel@lists.infradead.org
Cc: Michael Turquette <mturquette@baylibre.com >
Cc: Stephen Boyd <sboyd@kernel.org >
Cc: linux-clk@vger.kernel.org
Link: https://lore.kernel.org/r/20240115001255.4124-1-rdunlap@infradead.org
Reviewed-by: Nishanth Menon <nm@ti.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 21:47:41 -08:00
Eddie James
56ce4e733c
clk: ast2600: Add FSI parent clock with correct rate
...
In order to calculate correct FSI bus clocks, the FSI clock must
correctly calculate the rate from the parent (APLL / 4).
Signed-off-by: Eddie James <eajames@linux.ibm.com >
Link: https://lore.kernel.org/r/20240215220759.976998-3-eajames@linux.ibm.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 21:46:13 -08:00
Eddie James
692678b69c
dt-bindings: clock: ast2600: Add FSI clock
...
Add a definition for the FSI clock.
Signed-off-by: Eddie James <eajames@linux.ibm.com >
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20240215220759.976998-2-eajames@linux.ibm.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 21:45:45 -08:00
Colin Ian King
d71e1f5b10
clk: cdce925: Remove redundant assignment to variable 'rate'
...
The variable 'rate' being assigned a value that is never read, the
assignment is redundant and can be removed.
Cleans up clang scan build warning:
drivers/clk/clk-cdce925.c:104:3: warning: Value stored to 'rate' is
never read [deadcode.DeadStores]
Signed-off-by: Colin Ian King <colin.i.king@gmail.com >
Link: https://lore.kernel.org/r/20240216140132.2108665-1-colin.i.king@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 21:36:09 -08:00
Shradha Todi
265b07df75
clk: Provide managed helper to get and enable bulk clocks
...
Provide a managed devm_clk_bulk* wrapper to get and enable all
bulk clocks in order to simplify drivers that keeps all clocks
enabled for the time of driver operation.
Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com >
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com >
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org >
Signed-off-by: Shradha Todi <shradha.t@samsung.com >
Link: https://lore.kernel.org/r/20240220084046.23786-2-shradha.t@samsung.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 21:13:36 -08:00
Frank Wunderlich
7fcf1ef84f
clk: mediatek: add infracfg reset controller for mt7988
...
Infracfg can also operate as reset controller, add support for it.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20240201182409.39878-3-linux@fw-web.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 21:03:17 -08:00
Frank Wunderlich
c9d9bea92c
dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs
...
Add reset constants for using as index in driver and dts.
Value is starting again from 0 because resets are used in another device
than existing constants.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Link: https://lore.kernel.org/r/20240201182409.39878-2-linux@fw-web.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 21:03:17 -08:00
Rafał Miłecki
0a0156fe6e
dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clock
...
This helps validating DTS files. Introduced changes:
1. Documented "reg" property
2. Dropped "syscon" as it was incorrectly used
3. Adjusted nodename, "compatible" and "reg" in example
Signed-off-by: Rafał Miłecki <rafal@milecki.pl >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20240214061233.24645-4-zajec5@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:56:37 -08:00
Rafał Miłecki
e77c6359a4
dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock
...
This helps validating DTS files. Introduced changes:
1. Documented "reg" property
2. Dropped "syscon" as it was incorrectly used
3. Adjusted nodename, "compatible" and "reg" in example
Signed-off-by: Rafał Miłecki <rafal@milecki.pl >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20240214061233.24645-3-zajec5@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:56:37 -08:00
Rafał Miłecki
1e365996b2
dt-bindings: clock: mediatek: convert hifsys to the json-schema clock
...
This helps validating DTS files. Introduced changes:
1. Documented "reg" property
2. Documented "#reset-cells" property
3. Dropped "syscon" as it was incorrectly used
4. Adjusted "compatible" and "reg" in example
Signed-off-by: Rafał Miłecki <rafal@milecki.pl >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20240214061233.24645-2-zajec5@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:56:37 -08:00
Daniel Golle
aa690050c0
clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
...
Without the SGM_REG_SEL clock enabled the cpu freezes if trying to
access registers used by MT7981 clock drivers itself.
Mark SGM_REG_SEL as critical to make sure it is always enabled to
prevent freezes on boot even if the Ethernet driver which prepares
and enables the clock is not loaded or probed at a later point.
Fixes: 813c3b53b5daniel@makrotopia.org >
Link: https://lore.kernel.org/r/fc157139e6b7f8dfb6430ac7191ba754027705e8.1708221995.git.daniel@makrotopia.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:55:50 -08:00
Chen-Yu Tsai
a65083fa66
clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF
...
CLK_INFRA_SSPM_32K_SELF has the "f_f26m_ck" clock assigned as its parent.
This is inconsistent as the clock is part of a group that are all gates
without dividers, and this makes the kernel think it runs at 26 MHz.
After clarification from MediaTek engineers, the correct parent is
actually the system 32 KHz clock.
Fixes: 1eb8d61ac5wenst@chromium.org >
Link: https://lore.kernel.org/r/20240219105125.956278-1-wenst@chromium.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:55:30 -08:00
Christophe JAILLET
a32e88f2b2
clk: mediatek: mt7622-apmixedsys: Fix an error handling path in clk_mt8135_apmixed_probe()
...
'clk_data' is allocated with mtk_devm_alloc_clk_data(). So calling
mtk_free_clk_data() explicitly in the remove function would lead to a
double-free.
Remove the redundant call.
Fixes: c50e2ea650christophe.jaillet@wanadoo.fr >
Link: https://lore.kernel.org/r/2c553c2a5077757e4f7af0bb895acc43881cf62c.1704616152.git.christophe.jaillet@wanadoo.fr
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:51:57 -08:00
Christophe JAILLET
03c1c51eba
clk: mediatek: mt8135: Fix an error handling path in clk_mt8135_apmixed_probe()
...
If an error occurs after mtk_alloc_clk_data(), mtk_free_clk_data() should
be called, as already done in the remove function.
Fixes: 54b7026f01christophe.jaillet@wanadoo.fr >
Link: https://lore.kernel.org/r/6cd6af61e5a91598068227f1f68cfcfde1507453.1704615011.git.christophe.jaillet@wanadoo.fr
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:51:33 -08:00
Erick Archer
252c31a90e
clk: hisilicon: Use devm_kcalloc() instead of devm_kzalloc()
...
As noted in the "Deprecated Interfaces, Language Features, Attributes,
and Conventions" documentation [1], size calculations (especially
multiplication) should not be performed in memory allocator (or similar)
function arguments due to the risk of them overflowing. This could lead
to values wrapping around and a smaller allocation being made than the
caller was expecting. Using those allocations could lead to linear
overflows of heap memory and other misbehaviors.
So, use the purpose specific devm_kcalloc() function instead of the
argument size * count in the devm_kzalloc() function.
Link: https://www.kernel.org/doc/html/next/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments [1]
Link: https://github.com/KSPP/linux/issues/162
Signed-off-by: Erick Archer <erick.archer@gmx.com >
Link: https://lore.kernel.org/r/20240121142946.2796-1-erick.archer@gmx.com
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de >
Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:27:19 -08:00
Christophe JAILLET
64c6a38136
clk: hisilicon: hi3559a: Fix an erroneous devm_kfree()
...
'p_clk' is an array allocated just before the for loop for all clk that
need to be registered.
It is incremented at each loop iteration.
If a clk_register() call fails, 'p_clk' may point to something different
from what should be freed.
The best we can do, is to avoid this wrong release of memory.
Fixes: 6c81966107christophe.jaillet@wanadoo.fr >
Link: https://lore.kernel.org/r/773fc8425c3b8f5b0ca7c1d89f15b65831a85ca9.1705850155.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:26:39 -08:00
Christophe JAILLET
74e39f526d
clk: hisilicon: hi3519: Release the correct number of gates in hi3519_clk_unregister()
...
The gates are stored in 'hi3519_gate_clks', not 'hi3519_mux_clks'.
This is also in line with how hisi_clk_register_gate() is called in the
probe.
Fixes: 224b3b262cchristophe.jaillet@wanadoo.fr >
Link: https://lore.kernel.org/r/c3f1877c9a0886fa35c949c8f0ef25547f284f18.1704912510.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:23:48 -08:00
Sekhar Nori
44042fb0d6
MAINTAINERS: drop Sekhar Nori
...
My TI e-mail address will become inactive soon. Drop it.
Add an entry to CREDITS file for work done on TI DaVinci
family SoCs.
Signed-off-by: Sekhar Nori <nsekhar@ti.com >
Acked-by: Nishanth Menon <nm@ti.com >
Link: https://lore.kernel.org/r/20240131093434.55652-1-nsekhar@ti.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-02-21 20:20:02 -08:00
Cong Dang
81a7a88a98
clk: renesas: r8a779h0: Add RPC-IF clock
...
Add the module clock used by the SPI Multi I/O Bus Controller (RPC-IF)
on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com >
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/07a72378ca64b44341af960f042a6efd41d10dc3.1708354355.git.geert+renesas@glider.be
2024-02-20 11:37:34 +01:00
Cong Dang
ce77231863
clk: renesas: r8a779h0: Add SYS-DMAC clocks
...
Add the module clocks used by the Direct Memory Access Controllers for
System (SYS-DMAC) on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com >
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/0285ef5d0c0c9d232e196559c9130ab46733d7f7.1707915706.git.geert+renesas@glider.be
2024-02-20 11:37:31 +01:00
Cong Dang
9c579c36e9
clk: renesas: r8a779h0: Add SDHI clock
...
Add the SDHI module clock, which is used by the SD Card/MMC Interface on
the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com >
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/3a604a6924043775c2ed0630b1c5c29be2d1a5b9.1707915642.git.geert+renesas@glider.be
2024-02-20 11:37:28 +01:00
Cong Dang
e89ea92f53
clk: renesas: r8a779h0: Add EtherAVB clocks
...
Add the module clocks used by the Ethernet AVB (EtherAVB-IF) blocks on
the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com >
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Link: https://lore.kernel.org/r/a5b4252d9822ded3fd523bc35417306cae2ec2bd.1707661303.git.geert+renesas@glider.be
2024-02-20 11:32:35 +01:00
Stephen Boyd
a24f93f13e
Merge tag 'renesas-clk-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
...
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Ignore all clocks which are assigned to a non-Linux system
- Add watchdog clock on RZ/G3S
- Add camera (CRU) clock and reset on RZ/G2UL
- Add support for the R-Car V4M (R8A779H0) SoC
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779h0: Add I2C clocks
clk: renesas: r8a779h0: Add watchdog clock
clk: renesas: r8a779h0: Add PFC/GPIO clocks
clk: renesas: r8a779g0: Fix PCIe clock name
clk: renesas: cpg-mssr: Add support for R-Car V4M
clk: renesas: rcar-gen4: Add support for FRQCRC1
clk: renesas: r9a07g043: Add clock and reset entries for CRU
clk: renesas: r9a08g045: Add clock and reset support for watchdog
dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support
dt-bindings: power: Add r8a779h0 SYSC power domain definitions
dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support
clk: renesas: mstp: Remove obsolete clkdev registration
clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux system
of: Add for_each_reserved_child_of_node()
of: Add of_get_next_status_child() and makes more generic of_get_next
of: Add __of_device_is_status() and makes more generic status check
2024-02-19 11:16:32 -08:00
Claudiu Beznea
46fb5dd9ca
clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
...
Fix typo for sel_shdi variable.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com >
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be >
Link: https://lore.kernel.org/r/20240131102930.1841901-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2024-02-13 17:13:25 +01:00
Claudiu Beznea
9b2a11c838
clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux
...
The status configuration for SD1 mux clock is SEL_SDHI1_STS. Fix it.
Fixes: 16b86e5c03hien.huynh.px@renesas.com >
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com >
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be >
Link: https://lore.kernel.org/r/20240131102930.1841901-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2024-02-13 17:13:25 +01:00
Geert Uytterhoeven
d1b32a83a0
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
...
According to the R-Car S4 Series Hardware User’s Manual Rev.0.81, the
parent clock of the Pin Function (PFC/GPIO) module clock is the CP
clock.
As this clock is not documented to exist on R-Car S4, use the CPEX clock
instead.
Fixes: 73421f2a48geert+renesas@glider.be >
Link: https://lore.kernel.org/r/f88ec4aede0eaf0107c8bb7b28ba719ac6cd418f.1706197415.git.geert+renesas@glider.be
2024-02-13 17:13:25 +01:00
Geert Uytterhoeven
abb3fa662b
clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
...
According to the R-Car V4H Series Hardware User’s Manual Rev.1.00, the
parent clock of the Pin Function (PFC/GPIO) module clocks is the CP
clock.
Fix this by adding the missing CP clock, and correcting the PFC parents.
Fixes: f2afa78d5a36ff366033geert+renesas@glider.be >
Link: https://lore.kernel.org/r/5401fccd204dc90b44f0013e7f53b9eff8df8214.1706197297.git.geert+renesas@glider.be
2024-02-13 17:10:26 +01:00
Cong Dang
5aaa139b9a
clk: renesas: r8a779h0: Add I2C clocks
...
Add the module clocks used by the I2C Bus Interfaces on the Renesas
R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com >
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/7a76dadbce24c81dd2bee68765a0b41beca2d565.1706790236.git.geert+renesas@glider.be
2024-02-06 11:20:12 +01:00
Cong Dang
6e8b1dcb09
clk: renesas: r8a779h0: Add watchdog clock
...
Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com >
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/f1dbf0f3f484015f2e629d78b746cf377d6f6746.1706790015.git.geert+renesas@glider.be
2024-02-06 11:20:02 +01:00
Cong Dang
62527c9d46
clk: renesas: r8a779h0: Add PFC/GPIO clocks
...
Add the module clocks used by the Pin Function Controller (PFC) and
General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4M
(R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com >
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se >
Link: https://lore.kernel.org/r/a7d8f4111b87decb825db5ed310de8294f90b9f9.1706266196.git.geert+renesas@glider.be
2024-02-06 11:19:45 +01:00
Geert Uytterhoeven
096311157d
clk: renesas: r8a779g0: Fix PCIe clock name
...
Fix a typo in the name of the module clock for the second PCIe channel.
Fixes: 5ab16198b4geert+renesas@glider.be >
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/f582067564f357e2183d3db67b217084ecb51888.1706608032.git.geert+renesas@glider.be
2024-01-31 11:19:24 +01:00
Cong Dang
f077cab34d
clk: renesas: cpg-mssr: Add support for R-Car V4M
...
Initial CPG support for the R-Car V4M (R8A779H0).
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com >
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se >
Link: https://lore.kernel.org/r/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be
2024-01-31 11:19:21 +01:00
Geert Uytterhoeven
ad3393fefd
clk: renesas: rcar-gen4: Add support for FRQCRC1
...
R-Car V4H and V4M have a second Frequency Control Register C.
Add support for this by treating bit field offsets beyond 31 as
referring to the second register.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se >
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com >
Link: https://lore.kernel.org/r/f64d5573a92a18505619ff0ff808d50cfc2bde55.1706194617.git.geert+renesas@glider.be
2024-01-31 11:19:21 +01:00
Geert Uytterhoeven
775e7c4d36
Merge tag 'renesas-r8a779h0-dt-binding-defs-tag' into renesas-clk-for-v6.9
...
Renesas R-Car V4M DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car V4M (R8A779H0)
SoC, shared by driver and DT source files.
2024-01-31 11:19:12 +01:00
Biju Das
78ed252953
clk: renesas: r9a07g043: Add clock and reset entries for CRU
...
Add CRU clock and reset entries to CPG driver.
CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
sequence for the CRU block hence add these clocks to
r9a07g043_no_pm_mod_clks[] array and pass it as part of CPG data for
RZ/G2UL SoCs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be >
Link: https://lore.kernel.org/r/20240123114415.290918-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2024-01-31 11:14:53 +01:00
