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drm/amd/swsmu: Move IP specific functions

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Move SMU v15_0_0 specific functions to IP file
- smu_v15_0_0_set_default_dpm_tables and
- smu_v15_0_0_update_table

Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Pratik Vishwakarma
2026-02-11 08:35:30 +00:00
committed by Alex Deucher
parent b18fc0ab83
commit f38bb9b092
3 changed files with 67 additions and 74 deletions
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7
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
View File

@@ -226,8 +226,6 @@ int smu_v15_0_deep_sleep_control(struct smu_context *smu,
int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu);
int smu_v15_0_set_default_dpm_tables(struct smu_context *smu);
int smu_v15_0_get_pptable_from_firmware(struct smu_context *smu,
void **table,
uint32_t *size,
@@ -241,10 +239,5 @@ int smu_v15_0_enable_thermal_alert(struct smu_context *smu);
int smu_v15_0_disable_thermal_alert(struct smu_context *smu);
int smu_v15_0_0_update_table(struct smu_context *smu,
enum smu_table_id table_index,
int argument, void *table_data,
bool drv2smu);
#endif
#endif

66
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
View File

@@ -1726,72 +1726,6 @@ int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu)
return ret;
}
int smu_v15_0_0_update_table(struct smu_context *smu,
enum smu_table_id table_index,
int argument,
void *table_data,
bool drv2smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct amdgpu_device *adev = smu->adev;
struct smu_table *table = &smu_table->driver_table;
int table_id = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_TABLE,
table_index);
uint64_t address;
uint32_t table_size;
int ret;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0)
return -EINVAL;
table_size = smu_table->tables[table_index].size;
if (drv2smu) {
memcpy(table->cpu_addr, table_data, table_size);
/*
* Flush hdp cache: to guard the content seen by
* GPU is consitent with CPU.
*/
amdgpu_hdp_flush(adev, NULL);
}
address = table->mc_address;
struct smu_msg_args args = {
.msg = drv2smu ?
SMU_MSG_TransferTableDram2Smu :
SMU_MSG_TransferTableSmu2Dram,
.num_args = 3,
.num_out_args = 0,
};
args.args[0] = table_id;
args.args[1] = (uint32_t)lower_32_bits(address);
args.args[2] = (uint32_t)upper_32_bits(address);
ret = ctl->ops->send_msg(ctl, &args);
if (ret)
return ret;
if (!drv2smu) {
amdgpu_hdp_invalidate(adev, NULL);
memcpy(table_data, table->cpu_addr, table_size);
}
return 0;
}
int smu_v15_0_set_default_dpm_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
return smu_v15_0_0_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
smu_table->clocks_table, false);
}
int smu_v15_0_od_edit_dpm_table(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
long input[], uint32_t size)

68
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
View File

@@ -233,6 +233,72 @@ static int smu_v15_0_0_system_features_control(struct smu_context *smu, bool en)
return ret;
}
static int smu_v15_0_0_update_table(struct smu_context *smu,
enum smu_table_id table_index,
int argument,
void *table_data,
bool drv2smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct amdgpu_device *adev = smu->adev;
struct smu_table *table = &smu_table->driver_table;
int table_id = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_TABLE,
table_index);
uint64_t address;
uint32_t table_size;
int ret;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0)
return -EINVAL;
table_size = smu_table->tables[table_index].size;
if (drv2smu) {
memcpy(table->cpu_addr, table_data, table_size);
/*
* Flush hdp cache: to guard the content seen by
* GPU is consitent with CPU.
*/
amdgpu_hdp_flush(adev, NULL);
}
address = table->mc_address;
struct smu_msg_args args = {
.msg = drv2smu ?
SMU_MSG_TransferTableDram2Smu :
SMU_MSG_TransferTableSmu2Dram,
.num_args = 3,
.num_out_args = 0,
};
args.args[0] = table_id;
args.args[1] = (uint32_t)lower_32_bits(address);
args.args[2] = (uint32_t)upper_32_bits(address);
ret = ctl->ops->send_msg(ctl, &args);
if (ret)
return ret;
if (!drv2smu) {
amdgpu_hdp_invalidate(adev, NULL);
memcpy(table_data, table->cpu_addr, table_size);
}
return 0;
}
static int smu_v15_0_0_set_default_dpm_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
return smu_v15_0_0_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
smu_table->clocks_table, false);
}
static int smu_v15_0_0_get_metrics_table(struct smu_context *smu,
void *metrics_table,
bool bypass_cache)
@@ -1357,7 +1423,7 @@ static const struct pptable_funcs smu_v15_0_0_ppt_funcs = {
.system_features_control = smu_v15_0_0_system_features_control,
.dpm_set_vcn_enable = smu_v15_0_set_vcn_enable,
.dpm_set_jpeg_enable = smu_v15_0_set_jpeg_enable,
.set_default_dpm_table = smu_v15_0_set_default_dpm_tables,
.set_default_dpm_table = smu_v15_0_0_set_default_dpm_tables,
.read_sensor = smu_v15_0_0_read_sensor,
.is_dpm_running = smu_v15_0_0_is_dpm_running,
.set_watermarks_table = smu_v15_0_0_set_watermarks_table,