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drm/xe/multi_queue: Add multi_queue_enable_mask to gt information

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Add multi_queue_enable_mask field to the gt information structure
which is bitmask of all engine classes with multi queue support
enabled.

v2: Rename multi_queue_enable_mask to multi_queue_engine_class_mask
    (Matt Brost)

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20251211010249.1647839-20-niranjana.vishwanathapura@intel.com
This commit is contained in:
Niranjana Vishwanathapura
2025-12-10 17:02:49 -08:00
parent 7319c2ceb2
commit ee26c3b276
4 changed files with 9 additions and 0 deletions
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2
drivers/gpu/drm/xe/xe_debugfs.c
View File

@@ -93,6 +93,8 @@ static int info(struct seq_file *m, void *data)
xe_force_wake_ref(gt_to_fw(gt), XE_FW_GT));
drm_printf(&p, "gt%d engine_mask 0x%llx\n", id,
gt->info.engine_mask);
drm_printf(&p, "gt%d multi_queue_engine_class_mask 0x%x\n", id,
gt->info.multi_queue_engine_class_mask);
}
return 0;

5
drivers/gpu/drm/xe/xe_gt_types.h
View File

@@ -140,6 +140,11 @@ struct xe_gt {
u64 engine_mask;
/** @info.gmdid: raw GMD_ID value from hardware */
u32 gmdid;
/**
* @multi_queue_engine_class_mask: Bitmask of engine classes with
* multi queue support enabled.
*/
u16 multi_queue_engine_class_mask;
/** @info.id: Unique ID of this GT within the PCI Device */
u8 id;
/** @info.has_indirect_ring_state: GT has indirect ring state support */

1
drivers/gpu/drm/xe/xe_pci.c
View File

@@ -764,6 +764,7 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
gt->info.type = XE_GT_TYPE_MAIN;
gt->info.id = tile->id * xe->info.max_gt_per_tile;
gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask;
gt->info.engine_mask = graphics_desc->hw_engine_mask;
/*

1
drivers/gpu/drm/xe/xe_pci_types.h
View File

@@ -60,6 +60,7 @@ struct xe_device_desc {
struct xe_graphics_desc {
u64 hw_engine_mask; /* hardware engines provided by graphics IP */
u16 multi_queue_engine_class_mask; /* bitmask of engine classes which support multi queue */
u8 has_asid:1;
u8 has_atomic_enable_pte_bit:1;