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iio: adc: Add support for ad4062
The AD4060/AD4062 are versatile, 16-bit/12-bit, successive approximation register (SAR) analog-to-digital converter (ADC) with low-power and threshold monitoring modes. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Jorge Marques
committed by
Jonathan Cameron
Jonathan Cameron
parent
1b1ddab024
commit
d5284402d2
@@ -1439,6 +1439,7 @@ S: Supported
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W: https://ez.analog.com/linux-software-drivers
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F: Documentation/devicetree/bindings/iio/adc/adi,ad4062.yaml
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F: Documentation/iio/ad4062.rst
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F: drivers/iio/adc/ad4062.c
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ANALOG DEVICES INC AD4080 DRIVER
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M: Antoniu Miclaus <antoniu.miclaus@analog.com>
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@@ -70,6 +70,17 @@ config AD4030
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To compile this driver as a module, choose M here: the module will be
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called ad4030.
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config AD4062
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tristate "Analog Devices AD4062 Driver"
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depends on I3C
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select REGMAP_I3C
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help
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Say yes here to build support for Analog Devices AD4062 I3C analog
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to digital converters (ADC).
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To compile this driver as a module, choose M here: the module will be
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called ad4062.
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config AD4080
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tristate "Analog Devices AD4080 high speed ADC"
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depends on SPI
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@@ -11,6 +11,7 @@ obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o
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obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o
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obj-$(CONFIG_AD4000) += ad4000.o
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obj-$(CONFIG_AD4030) += ad4030.o
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obj-$(CONFIG_AD4062) += ad4062.o
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obj-$(CONFIG_AD4080) += ad4080.o
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obj-$(CONFIG_AD4130) += ad4130.o
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obj-$(CONFIG_AD4170_4) += ad4170-4.o
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819
drivers/iio/adc/ad4062.c
Normal file
819
drivers/iio/adc/ad4062.c
Normal file
@@ -0,0 +1,819 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Analog Devices AD4062 I3C ADC driver
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*
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* Copyright 2025 Analog Devices Inc.
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*/
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#include <linux/array_size.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/i3c/device.h>
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#include <linux/i3c/master.h>
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#include <linux/iio/iio.h>
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#include <linux/interrupt.h>
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#include <linux/jiffies.h>
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#include <linux/math.h>
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#include <linux/minmax.h>
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#include <linux/pm_runtime.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/units.h>
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#include <linux/unaligned.h>
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#include <linux/util_macros.h>
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#define AD4062_REG_INTERFACE_CONFIG_A 0x00
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#define AD4062_REG_DEVICE_CONFIG 0x02
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#define AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK GENMASK(1, 0)
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#define AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE 3
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#define AD4062_REG_PROD_ID_1 0x05
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#define AD4062_REG_DEVICE_GRADE 0x06
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#define AD4062_REG_SCRATCH_PAD 0x0A
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#define AD4062_REG_VENDOR_H 0x0D
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#define AD4062_REG_STREAM_MODE 0x0E
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#define AD4062_REG_INTERFACE_STATUS 0x11
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#define AD4062_REG_MODE_SET 0x20
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#define AD4062_REG_MODE_SET_ENTER_ADC BIT(0)
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#define AD4062_REG_ADC_MODES 0x21
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#define AD4062_REG_ADC_MODES_MODE_MSK GENMASK(1, 0)
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#define AD4062_REG_ADC_CONFIG 0x22
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#define AD4062_REG_ADC_CONFIG_REF_EN_MSK BIT(5)
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#define AD4062_REG_ADC_CONFIG_SCALE_EN_MSK BIT(4)
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#define AD4062_REG_AVG_CONFIG 0x23
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#define AD4062_REG_GP_CONF 0x24
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#define AD4062_REG_GP_CONF_MODE_MSK_1 GENMASK(6, 4)
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#define AD4062_REG_INTR_CONF 0x25
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#define AD4062_REG_INTR_CONF_EN_MSK_1 GENMASK(5, 4)
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#define AD4062_REG_TIMER_CONFIG 0x27
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#define AD4062_REG_TIMER_CONFIG_FS_MASK GENMASK(7, 4)
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#define AD4062_REG_MON_VAL 0x2F
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#define AD4062_REG_ADC_IBI_EN 0x31
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#define AD4062_REG_ADC_IBI_EN_CONV_TRIGGER BIT(2)
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#define AD4062_REG_FUSE_CRC 0x40
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#define AD4062_REG_DEVICE_STATUS 0x41
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#define AD4062_REG_DEVICE_STATUS_DEVICE_RESET BIT(6)
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#define AD4062_REG_IBI_STATUS 0x48
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#define AD4062_REG_CONV_READ_LSB 0x50
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#define AD4062_REG_CONV_TRIGGER_32BITS 0x59
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#define AD4062_REG_CONV_AUTO 0x61
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#define AD4062_MAX_REG AD4062_REG_CONV_AUTO
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#define AD4062_MON_VAL_MIDDLE_POINT 0x8000
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#define AD4062_I3C_VENDOR 0x0177
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#define AD4062_SOFT_RESET 0x81
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#define AD4060_PROD_ID 0x7A
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#define AD4062_PROD_ID 0x7C
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#define AD4062_GP_DRDY 0x2
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#define AD4062_INTR_EN_NEITHER 0x0
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#define AD4062_TCONV_NS 270
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enum ad4062_operation_mode {
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AD4062_SAMPLE_MODE = 0x0,
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AD4062_BURST_AVERAGING_MODE = 0x1,
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AD4062_MONITOR_MODE = 0x3,
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};
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struct ad4062_chip_info {
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const struct iio_chan_spec channels[1];
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const char *name;
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u16 prod_id;
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u16 avg_max;
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};
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enum {
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AD4062_SCAN_TYPE_SAMPLE,
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AD4062_SCAN_TYPE_BURST_AVG,
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};
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static const unsigned int ad4062_conversion_freqs[] = {
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2000000, 1000000, 300000, 100000, /* 0 - 3 */
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33300, 10000, 3000, 500, /* 4 - 7 */
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333, 250, 200, 166, /* 8 - 11 */
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140, 124, 111, /* 12 - 15 */
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};
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struct ad4062_state {
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const struct ad4062_chip_info *chip;
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const struct ad4062_bus_ops *ops;
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enum ad4062_operation_mode mode;
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struct completion completion;
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struct iio_trigger *trigger;
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struct iio_dev *indio_dev;
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struct i3c_device *i3cdev;
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struct regmap *regmap;
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int vref_uV;
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unsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)];
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u16 sampling_frequency;
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u8 oversamp_ratio;
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u8 conv_addr;
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union {
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__be32 be32;
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__be16 be16;
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} buf __aligned(IIO_DMA_MINALIGN);
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};
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static const struct regmap_range ad4062_regmap_rd_ranges[] = {
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regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_GRADE),
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regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_INTERFACE_STATUS),
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regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN),
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regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_IBI_STATUS),
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regmap_reg_range(AD4062_REG_CONV_READ_LSB, AD4062_REG_CONV_AUTO),
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};
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static const struct regmap_access_table ad4062_regmap_rd_table = {
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.yes_ranges = ad4062_regmap_rd_ranges,
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.n_yes_ranges = ARRAY_SIZE(ad4062_regmap_rd_ranges),
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};
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static const struct regmap_range ad4062_regmap_wr_ranges[] = {
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regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_CONFIG),
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regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_SCRATCH_PAD),
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regmap_reg_range(AD4062_REG_STREAM_MODE, AD4062_REG_INTERFACE_STATUS),
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regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN),
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regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_DEVICE_STATUS),
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};
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static const struct regmap_access_table ad4062_regmap_wr_table = {
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.yes_ranges = ad4062_regmap_wr_ranges,
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.n_yes_ranges = ARRAY_SIZE(ad4062_regmap_wr_ranges),
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};
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#define AD4062_CHAN { \
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.type = IIO_VOLTAGE, \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_CALIBSCALE) | \
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BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
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.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.indexed = 1, \
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.channel = 0, \
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}
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static const struct ad4062_chip_info ad4060_chip_info = {
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.name = "ad4060",
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.channels = { AD4062_CHAN },
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.prod_id = AD4060_PROD_ID,
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.avg_max = 256,
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};
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static const struct ad4062_chip_info ad4062_chip_info = {
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.name = "ad4062",
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.channels = { AD4062_CHAN },
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.prod_id = AD4062_PROD_ID,
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.avg_max = 4096,
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};
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static int ad4062_set_oversampling_ratio(struct ad4062_state *st, int val, int val2)
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{
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const u32 _max = st->chip->avg_max;
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const u32 _min = 1;
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int ret;
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if (!in_range(val, _min, _max) || val2 != 0)
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return -EINVAL;
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/* 1 disables oversampling */
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val = ilog2(val);
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if (val == 0) {
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st->mode = AD4062_SAMPLE_MODE;
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} else {
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st->mode = AD4062_BURST_AVERAGING_MODE;
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ret = regmap_write(st->regmap, AD4062_REG_AVG_CONFIG, val - 1);
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if (ret)
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return ret;
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}
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st->oversamp_ratio = val;
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return 0;
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}
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static int ad4062_get_oversampling_ratio(struct ad4062_state *st, int *val)
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{
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int ret, buf;
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if (st->mode == AD4062_SAMPLE_MODE) {
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*val = 1;
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return 0;
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}
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ret = regmap_read(st->regmap, AD4062_REG_AVG_CONFIG, &buf);
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if (ret)
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return ret;
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*val = BIT(buf + 1);
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return 0;
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}
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static int ad4062_calc_sampling_frequency(unsigned int fosc, unsigned int oversamp_ratio)
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{
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/* From datasheet p.31: (n_avg - 1)/fosc + tconv */
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u32 n_avg = BIT(oversamp_ratio) - 1;
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u32 period_ns = NSEC_PER_SEC / fosc;
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/* Result is less than 1 Hz */
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if (n_avg >= fosc)
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return 1;
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return NSEC_PER_SEC / (n_avg * period_ns + AD4062_TCONV_NS);
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}
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static int ad4062_populate_sampling_frequency(struct ad4062_state *st)
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{
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for (u8 i = 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++)
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st->samp_freqs[i] =
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ad4062_calc_sampling_frequency(ad4062_conversion_freqs[i],
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st->oversamp_ratio);
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return 0;
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}
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static int ad4062_get_sampling_frequency(struct ad4062_state *st, int *val)
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{
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int freq = ad4062_conversion_freqs[st->sampling_frequency];
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*val = ad4062_calc_sampling_frequency(freq, st->oversamp_ratio);
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return IIO_VAL_INT;
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}
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static int ad4062_set_sampling_frequency(struct ad4062_state *st, int val, int val2)
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{
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int ret;
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if (val2 != 0)
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return -EINVAL;
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ret = ad4062_populate_sampling_frequency(st);
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if (ret)
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return ret;
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st->sampling_frequency =
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find_closest_descending(val, st->samp_freqs,
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ARRAY_SIZE(ad4062_conversion_freqs));
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return 0;
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}
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static int ad4062_check_ids(struct ad4062_state *st)
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{
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struct device *dev = &st->i3cdev->dev;
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int ret;
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u16 val;
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ret = regmap_bulk_read(st->regmap, AD4062_REG_PROD_ID_1,
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&st->buf.be16, sizeof(st->buf.be16));
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if (ret)
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return ret;
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val = be16_to_cpu(st->buf.be16);
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if (val != st->chip->prod_id)
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dev_warn(dev, "Production ID x%x does not match known values", val);
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ret = regmap_bulk_read(st->regmap, AD4062_REG_VENDOR_H,
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&st->buf.be16, sizeof(st->buf.be16));
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if (ret)
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return ret;
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val = be16_to_cpu(st->buf.be16);
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if (val != AD4062_I3C_VENDOR) {
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dev_err(dev, "Vendor ID x%x does not match expected value\n", val);
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return -ENODEV;
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}
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return 0;
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}
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static int ad4062_conversion_frequency_set(struct ad4062_state *st, u8 val)
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{
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return regmap_write(st->regmap, AD4062_REG_TIMER_CONFIG,
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FIELD_PREP(AD4062_REG_TIMER_CONFIG_FS_MASK, val));
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}
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static int ad4062_set_operation_mode(struct ad4062_state *st,
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enum ad4062_operation_mode mode)
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{
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int ret;
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ret = ad4062_conversion_frequency_set(st, st->sampling_frequency);
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if (ret)
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return ret;
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ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_MODES,
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AD4062_REG_ADC_MODES_MODE_MSK, mode);
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if (ret)
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return ret;
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return regmap_write(st->regmap, AD4062_REG_MODE_SET,
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AD4062_REG_MODE_SET_ENTER_ADC);
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}
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static int ad4062_soft_reset(struct ad4062_state *st)
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{
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u8 val = AD4062_SOFT_RESET;
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int ret;
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ret = regmap_write(st->regmap, AD4062_REG_INTERFACE_CONFIG_A, val);
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if (ret)
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return ret;
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/* Wait AD4062 treset time, datasheet p8 */
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ndelay(60);
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return 0;
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}
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static int ad4062_setup(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
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const bool *ref_sel)
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{
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struct ad4062_state *st = iio_priv(indio_dev);
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int ret;
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ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,
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AD4062_REG_GP_CONF_MODE_MSK_1,
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FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1,
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AD4062_GP_DRDY));
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if (ret)
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return ret;
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ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG,
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AD4062_REG_ADC_CONFIG_REF_EN_MSK,
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FIELD_PREP(AD4062_REG_ADC_CONFIG_REF_EN_MSK,
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*ref_sel));
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if (ret)
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return ret;
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ret = regmap_write(st->regmap, AD4062_REG_DEVICE_STATUS,
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AD4062_REG_DEVICE_STATUS_DEVICE_RESET);
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if (ret)
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return ret;
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ret = regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF,
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AD4062_REG_INTR_CONF_EN_MSK_1,
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FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_1,
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AD4062_INTR_EN_NEITHER));
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if (ret)
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return ret;
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st->buf.be16 = cpu_to_be16(AD4062_MON_VAL_MIDDLE_POINT);
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return regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL,
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&st->buf.be16, sizeof(st->buf.be16));
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}
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static irqreturn_t ad4062_irq_handler_drdy(int irq, void *private)
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{
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struct iio_dev *indio_dev = private;
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struct ad4062_state *st = iio_priv(indio_dev);
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complete(&st->completion);
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return IRQ_HANDLED;
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}
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|
||||
static void ad4062_ibi_handler(struct i3c_device *i3cdev,
|
||||
const struct i3c_ibi_payload *payload)
|
||||
{
|
||||
struct ad4062_state *st = i3cdev_get_drvdata(i3cdev);
|
||||
|
||||
complete(&st->completion);
|
||||
}
|
||||
|
||||
static void ad4062_disable_ibi(void *data)
|
||||
{
|
||||
struct i3c_device *i3cdev = data;
|
||||
|
||||
i3c_device_disable_ibi(i3cdev);
|
||||
}
|
||||
|
||||
static void ad4062_free_ibi(void *data)
|
||||
{
|
||||
struct i3c_device *i3cdev = data;
|
||||
|
||||
i3c_device_free_ibi(i3cdev);
|
||||
}
|
||||
|
||||
static int ad4062_request_ibi(struct i3c_device *i3cdev)
|
||||
{
|
||||
const struct i3c_ibi_setup ibireq = {
|
||||
.max_payload_len = 1,
|
||||
.num_slots = 1,
|
||||
.handler = ad4062_ibi_handler,
|
||||
};
|
||||
int ret;
|
||||
|
||||
ret = i3c_device_request_ibi(i3cdev, &ibireq);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = devm_add_action_or_reset(&i3cdev->dev, ad4062_free_ibi, i3cdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = i3c_device_enable_ibi(i3cdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return devm_add_action_or_reset(&i3cdev->dev, ad4062_disable_ibi, i3cdev);
|
||||
}
|
||||
|
||||
static int ad4062_request_irq(struct iio_dev *indio_dev)
|
||||
{
|
||||
struct ad4062_state *st = iio_priv(indio_dev);
|
||||
struct device *dev = &st->i3cdev->dev;
|
||||
int ret;
|
||||
|
||||
ret = fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp1");
|
||||
if (ret == -EPROBE_DEFER)
|
||||
return ret;
|
||||
|
||||
if (ret < 0)
|
||||
return regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN,
|
||||
AD4062_REG_ADC_IBI_EN_CONV_TRIGGER,
|
||||
AD4062_REG_ADC_IBI_EN_CONV_TRIGGER);
|
||||
|
||||
return devm_request_threaded_irq(dev, ret,
|
||||
ad4062_irq_handler_drdy,
|
||||
NULL, IRQF_ONESHOT, indio_dev->name,
|
||||
indio_dev);
|
||||
}
|
||||
|
||||
static const int ad4062_oversampling_avail[] = {
|
||||
1, 2, 4, 8, 16, 32, 64, 128, /* 0 - 7 */
|
||||
256, 512, 1024, 2048, 4096, /* 8 - 12 */
|
||||
};
|
||||
|
||||
static int ad4062_read_avail(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan, const int **vals,
|
||||
int *type, int *len, long mask)
|
||||
{
|
||||
struct ad4062_state *st = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
switch (mask) {
|
||||
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
|
||||
*vals = ad4062_oversampling_avail;
|
||||
*len = ARRAY_SIZE(ad4062_oversampling_avail);
|
||||
*len -= st->chip->avg_max == 256 ? 4 : 0;
|
||||
*type = IIO_VAL_INT;
|
||||
|
||||
return IIO_AVAIL_LIST;
|
||||
case IIO_CHAN_INFO_SAMP_FREQ:
|
||||
ret = ad4062_populate_sampling_frequency(st);
|
||||
if (ret)
|
||||
return ret;
|
||||
*vals = st->samp_freqs;
|
||||
*len = st->oversamp_ratio ? ARRAY_SIZE(ad4062_conversion_freqs) : 1;
|
||||
*type = IIO_VAL_INT;
|
||||
|
||||
return IIO_AVAIL_LIST;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int ad4062_get_chan_calibscale(struct ad4062_state *st, int *val, int *val2)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = regmap_bulk_read(st->regmap, AD4062_REG_MON_VAL,
|
||||
&st->buf.be16, sizeof(st->buf.be16));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* From datasheet: code out = code in × mon_val/0x8000 */
|
||||
*val = be16_to_cpu(st->buf.be16) * 2;
|
||||
*val2 = 16;
|
||||
|
||||
return IIO_VAL_FRACTIONAL_LOG2;
|
||||
}
|
||||
|
||||
static int ad4062_set_chan_calibscale(struct ad4062_state *st, int gain_int,
|
||||
int gain_frac)
|
||||
{
|
||||
/* Divide numerator and denumerator by known great common divider */
|
||||
const u32 mon_val = AD4062_MON_VAL_MIDDLE_POINT / 64;
|
||||
const u32 micro = MICRO / 64;
|
||||
const u32 gain_fp = gain_int * MICRO + gain_frac;
|
||||
const u32 reg_val = DIV_ROUND_CLOSEST(gain_fp * mon_val, micro);
|
||||
int ret;
|
||||
|
||||
/* Checks if the gain is in range and the value fits the field */
|
||||
if (gain_int < 0 || gain_int > 1 || reg_val > BIT(16) - 1)
|
||||
return -EINVAL;
|
||||
|
||||
st->buf.be16 = cpu_to_be16(reg_val);
|
||||
ret = regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL,
|
||||
&st->buf.be16, sizeof(st->buf.be16));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Enable scale if gain is not equal to one */
|
||||
return regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG,
|
||||
AD4062_REG_ADC_CONFIG_SCALE_EN_MSK,
|
||||
FIELD_PREP(AD4062_REG_ADC_CONFIG_SCALE_EN_MSK,
|
||||
!(gain_int == 1 && gain_frac == 0)));
|
||||
}
|
||||
|
||||
static int ad4062_read_chan_raw(struct ad4062_state *st, int *val)
|
||||
{
|
||||
struct i3c_device *i3cdev = st->i3cdev;
|
||||
struct i3c_priv_xfer xfer_trigger = {
|
||||
.data.out = &st->conv_addr,
|
||||
.len = sizeof(st->conv_addr),
|
||||
.rnw = false,
|
||||
};
|
||||
struct i3c_priv_xfer xfer_sample = {
|
||||
.data.in = &st->buf.be32,
|
||||
.len = sizeof(st->buf.be32),
|
||||
.rnw = true,
|
||||
};
|
||||
int ret;
|
||||
|
||||
PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm);
|
||||
ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ad4062_set_operation_mode(st, st->mode);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reinit_completion(&st->completion);
|
||||
/* Change address pointer to trigger conversion */
|
||||
st->conv_addr = AD4062_REG_CONV_TRIGGER_32BITS;
|
||||
ret = i3c_device_do_priv_xfers(i3cdev, &xfer_trigger, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
/*
|
||||
* Single sample read should be used only for oversampling and
|
||||
* sampling frequency pairs that take less than 1 sec.
|
||||
*/
|
||||
ret = wait_for_completion_timeout(&st->completion,
|
||||
msecs_to_jiffies(1000));
|
||||
if (!ret)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
ret = i3c_device_do_priv_xfers(i3cdev, &xfer_sample, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
*val = be32_to_cpu(st->buf.be32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ad4062_read_raw_dispatch(struct ad4062_state *st,
|
||||
int *val, int *val2, long info)
|
||||
{
|
||||
switch (info) {
|
||||
case IIO_CHAN_INFO_RAW:
|
||||
return ad4062_read_chan_raw(st, val);
|
||||
|
||||
case IIO_CHAN_INFO_CALIBSCALE:
|
||||
return ad4062_get_chan_calibscale(st, val, val2);
|
||||
|
||||
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
|
||||
return ad4062_get_oversampling_ratio(st, val);
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int ad4062_read_raw(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan,
|
||||
int *val, int *val2, long info)
|
||||
{
|
||||
struct ad4062_state *st = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
switch (info) {
|
||||
case IIO_CHAN_INFO_SAMP_FREQ:
|
||||
return ad4062_get_sampling_frequency(st, val);
|
||||
}
|
||||
|
||||
if (!iio_device_claim_direct(indio_dev))
|
||||
return -EBUSY;
|
||||
|
||||
ret = ad4062_read_raw_dispatch(st, val, val2, info);
|
||||
iio_device_release_direct(indio_dev);
|
||||
return ret ?: IIO_VAL_INT;
|
||||
}
|
||||
|
||||
static int ad4062_write_raw_dispatch(struct ad4062_state *st, int val, int val2,
|
||||
long info)
|
||||
{
|
||||
switch (info) {
|
||||
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
|
||||
return ad4062_set_oversampling_ratio(st, val, val2);
|
||||
|
||||
case IIO_CHAN_INFO_CALIBSCALE:
|
||||
return ad4062_set_chan_calibscale(st, val, val2);
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
};
|
||||
|
||||
static int ad4062_write_raw(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan, int val,
|
||||
int val2, long info)
|
||||
{
|
||||
struct ad4062_state *st = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
switch (info) {
|
||||
case IIO_CHAN_INFO_SAMP_FREQ:
|
||||
return ad4062_set_sampling_frequency(st, val, val2);
|
||||
}
|
||||
|
||||
if (!iio_device_claim_direct(indio_dev))
|
||||
return -EBUSY;
|
||||
|
||||
ret = ad4062_write_raw_dispatch(st, val, val2, info);
|
||||
|
||||
iio_device_release_direct(indio_dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg,
|
||||
unsigned int writeval, unsigned int *readval)
|
||||
{
|
||||
struct ad4062_state *st = iio_priv(indio_dev);
|
||||
|
||||
if (readval)
|
||||
return regmap_read(st->regmap, reg, readval);
|
||||
else
|
||||
return regmap_write(st->regmap, reg, writeval);
|
||||
}
|
||||
|
||||
static const struct iio_info ad4062_info = {
|
||||
.read_raw = ad4062_read_raw,
|
||||
.write_raw = ad4062_write_raw,
|
||||
.read_avail = ad4062_read_avail,
|
||||
.debugfs_reg_access = ad4062_debugfs_reg_access,
|
||||
};
|
||||
|
||||
static const struct regmap_config ad4062_regmap_config = {
|
||||
.name = "ad4062",
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
.max_register = AD4062_MAX_REG,
|
||||
.rd_table = &ad4062_regmap_rd_table,
|
||||
.wr_table = &ad4062_regmap_wr_table,
|
||||
.can_sleep = true,
|
||||
};
|
||||
|
||||
static int ad4062_regulators_get(struct ad4062_state *st, bool *ref_sel)
|
||||
{
|
||||
struct device *dev = &st->i3cdev->dev;
|
||||
int ret;
|
||||
|
||||
ret = devm_regulator_get_enable(dev, "vio");
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to enable vio voltage\n");
|
||||
|
||||
st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "ref");
|
||||
*ref_sel = st->vref_uV == -ENODEV;
|
||||
if (st->vref_uV < 0 && !*ref_sel)
|
||||
return dev_err_probe(dev, st->vref_uV,
|
||||
"Failed to enable and read ref voltage\n");
|
||||
|
||||
if (*ref_sel) {
|
||||
st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "vdd");
|
||||
if (st->vref_uV < 0)
|
||||
return dev_err_probe(dev, st->vref_uV,
|
||||
"Failed to enable and read vdd voltage\n");
|
||||
} else {
|
||||
ret = devm_regulator_get_enable(dev, "vdd");
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret,
|
||||
"Failed to enable vdd regulator\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i3c_device_id ad4062_id_table[] = {
|
||||
I3C_DEVICE(AD4062_I3C_VENDOR, AD4060_PROD_ID, &ad4060_chip_info),
|
||||
I3C_DEVICE(AD4062_I3C_VENDOR, AD4062_PROD_ID, &ad4062_chip_info),
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i3c, ad4062_id_table);
|
||||
|
||||
static int ad4062_probe(struct i3c_device *i3cdev)
|
||||
{
|
||||
const struct i3c_device_id *id = i3c_device_match_id(i3cdev, ad4062_id_table);
|
||||
const struct ad4062_chip_info *chip = id->data;
|
||||
struct device *dev = &i3cdev->dev;
|
||||
struct iio_dev *indio_dev;
|
||||
struct ad4062_state *st;
|
||||
bool ref_sel;
|
||||
int ret;
|
||||
|
||||
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
|
||||
if (!indio_dev)
|
||||
return -ENOMEM;
|
||||
|
||||
st = iio_priv(indio_dev);
|
||||
st->i3cdev = i3cdev;
|
||||
i3cdev_set_drvdata(i3cdev, st);
|
||||
init_completion(&st->completion);
|
||||
|
||||
ret = ad4062_regulators_get(st, &ref_sel);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
st->regmap = devm_regmap_init_i3c(i3cdev, &ad4062_regmap_config);
|
||||
if (IS_ERR(st->regmap))
|
||||
return dev_err_probe(dev, PTR_ERR(st->regmap),
|
||||
"Failed to initialize regmap\n");
|
||||
|
||||
st->mode = AD4062_SAMPLE_MODE;
|
||||
st->chip = chip;
|
||||
st->sampling_frequency = 0;
|
||||
st->oversamp_ratio = 0;
|
||||
st->indio_dev = indio_dev;
|
||||
|
||||
indio_dev->modes = INDIO_DIRECT_MODE;
|
||||
indio_dev->num_channels = 1;
|
||||
indio_dev->info = &ad4062_info;
|
||||
indio_dev->name = chip->name;
|
||||
indio_dev->channels = chip->channels;
|
||||
|
||||
ret = ad4062_soft_reset(st);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "AD4062 failed to soft reset\n");
|
||||
|
||||
ret = ad4062_check_ids(st);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ad4062_setup(indio_dev, indio_dev->channels, &ref_sel);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ad4062_request_irq(indio_dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pm_runtime_set_active(dev);
|
||||
ret = devm_pm_runtime_enable(dev);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to enable pm_runtime\n");
|
||||
|
||||
pm_runtime_set_autosuspend_delay(dev, 1000);
|
||||
pm_runtime_use_autosuspend(dev);
|
||||
|
||||
ret = ad4062_request_ibi(i3cdev);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to request i3c ibi\n");
|
||||
|
||||
return devm_iio_device_register(dev, indio_dev);
|
||||
}
|
||||
|
||||
static int ad4062_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct ad4062_state *st = dev_get_drvdata(dev);
|
||||
|
||||
return regmap_write(st->regmap, AD4062_REG_DEVICE_CONFIG,
|
||||
FIELD_PREP(AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK,
|
||||
AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE));
|
||||
}
|
||||
|
||||
static int ad4062_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct ad4062_state *st = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = regmap_clear_bits(st->regmap, AD4062_REG_DEVICE_CONFIG,
|
||||
AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Wait device functional blocks to power up */
|
||||
fsleep(3 * USEC_PER_MSEC);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static DEFINE_RUNTIME_DEV_PM_OPS(ad4062_pm_ops,
|
||||
ad4062_runtime_suspend, ad4062_runtime_resume, NULL);
|
||||
|
||||
static struct i3c_driver ad4062_driver = {
|
||||
.driver = {
|
||||
.name = "ad4062",
|
||||
.pm = pm_ptr(&ad4062_pm_ops),
|
||||
},
|
||||
.probe = ad4062_probe,
|
||||
.id_table = ad4062_id_table,
|
||||
};
|
||||
module_i3c_driver(ad4062_driver);
|
||||
|
||||
MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>");
|
||||
MODULE_DESCRIPTION("Analog Devices AD4062");
|
||||
MODULE_LICENSE("GPL");
|
||||
Reference in New Issue
Block a user