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drm/xe: Apply Wa_14020316580 in xe_gt_idle_enable_pg()

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Wa_14020316580 was getting clobbered by power gating init code
later in the driver load sequence. Move the Wa so that
it applies correctly.

Fixes: 7cd05ef89c ("drm/xe/xe2hpm: Add initial set of workarounds")
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251129052548.70766-1-vinay.belgaumkar@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit 8b55021453)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
This commit is contained in:
Vinay Belgaumkar
2025-11-28 21:25:48 -08:00
committed by Thomas Hellström
parent b32045d73b
commit c88a0731ed
3 changed files with 9 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/xe/xe_gt_idle.c
View File

@@ -5,6 +5,7 @@
#include <drm/drm_managed.h>
#include <generated/xe_wa_oob.h>
#include "xe_force_wake.h"
#include "xe_device.h"
#include "xe_gt.h"
@@ -16,6 +17,7 @@
#include "xe_mmio.h"
#include "xe_pm.h"
#include "xe_sriov.h"
#include "xe_wa.h"
/**
* DOC: Xe GT Idle
@@ -145,6 +147,12 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt)
xe_mmio_write32(mmio, RENDER_POWERGATE_IDLE_HYSTERESIS, 25);
}
if (XE_GT_WA(gt, 14020316580))
gtidle->powergate_enable &= ~(VDN_HCP_POWERGATE_ENABLE(0) |
VDN_MFXVDENC_POWERGATE_ENABLE(0) |
VDN_HCP_POWERGATE_ENABLE(2) |
VDN_MFXVDENC_POWERGATE_ENABLE(2));
xe_mmio_write32(mmio, POWERGATE_ENABLE, gtidle->powergate_enable);
xe_force_wake_put(gt_to_fw(gt), fw_ref);
}

8
drivers/gpu/drm/xe/xe_wa.c
View File

@@ -270,14 +270,6 @@ static const struct xe_rtp_entry_sr gt_was[] = {
XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
},
{ XE_RTP_NAME("14020316580"),
XE_RTP_RULES(MEDIA_VERSION(1301)),
XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
VDN_HCP_POWERGATE_ENABLE(0) |
VDN_MFXVDENC_POWERGATE_ENABLE(0) |
VDN_HCP_POWERGATE_ENABLE(2) |
VDN_MFXVDENC_POWERGATE_ENABLE(2))),
},
{ XE_RTP_NAME("14019449301"),
XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),

1
drivers/gpu/drm/xe/xe_wa_oob.rules
View File

@@ -76,3 +76,4 @@
15015404425_disable PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
16026007364 MEDIA_VERSION(3000)
14020316580 MEDIA_VERSION(1301)