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drm/amdkfd: fix partitioned gfx12 address watch enablement

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GFX 12 devices that support spatial partitioning should use the WREG32
per XCC macro when updating address watch settings, similar to GFX 9
devices that support spatial partitioning.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jonathan Kim
2025-09-08 17:40:01 +00:00
committed by Alex Deucher
parent a0806e7fe7
commit c14af4cc24
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
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@@ -347,13 +347,13 @@ static uint32_t kgd_gfx_v12_1_set_address_watch(struct amdgpu_device *adev,
VALID,
1);
WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_H) +
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_H) +
(watch_id * TCP_WATCH_STRIDE)),
watch_address_high);
watch_address_high, inst);
WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_L) +
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_L) +
(watch_id * TCP_WATCH_STRIDE)),
watch_address_low);
watch_address_low, inst);
return watch_address_cntl;
}