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drm/sun4i: layer: replace mixer with layer struct

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This allows to almost completely decouple layer code from mixer. This is
important for DE33.

Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
Tested-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20251104180942.61538-29-jernej.skrabec@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
This commit is contained in:
Jernej Skrabec
2025-11-04 19:09:40 +01:00
committed by Chen-Yu Tsai
parent d1fe263942
commit bb1d2ddee5
9 changed files with 66 additions and 67 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/sun4i/sun8i_csc.c
View File

@@ -233,14 +233,14 @@ void sun8i_csc_config(struct sun8i_layer *layer,
u32 mode = sun8i_csc_get_mode(state);
u32 base;
if (layer->mixer->cfg->de_type == SUN8I_MIXER_DE3) {
if (layer->cfg->de_type == SUN8I_MIXER_DE3) {
sun8i_de3_ccsc_setup(layer->regs, layer->channel,
mode, state->color_encoding,
state->color_range);
return;
}
base = ccsc_base[layer->mixer->cfg->lay_cfg.ccsc][layer->channel];
base = ccsc_base[layer->cfg->ccsc][layer->channel];
sun8i_csc_setup(layer->regs, base,
mode, state->color_encoding,

6
drivers/gpu/drm/sun4i/sun8i_mixer.c
View File

@@ -339,7 +339,8 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
layer = sun8i_vi_layer_init_one(drm, mixer, type,
mixer->engine.regs, i,
phy_index, plane_cnt);
phy_index, plane_cnt,
&mixer->cfg->lay_cfg);
if (IS_ERR(layer)) {
dev_err(drm->dev,
"Couldn't initialize overlay plane\n");
@@ -364,7 +365,8 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
layer = sun8i_ui_layer_init_one(drm, mixer, type,
mixer->engine.regs, index,
phy_index, plane_cnt);
phy_index, plane_cnt,
&mixer->cfg->lay_cfg);
if (IS_ERR(layer)) {
dev_err(drm->dev, "Couldn't initialize %s plane\n",
i ? "overlay" : "primary");

27
drivers/gpu/drm/sun4i/sun8i_mixer.h
View File

@@ -225,13 +225,14 @@ enum {
};
struct sun8i_layer {
struct drm_plane plane;
struct sun8i_mixer *mixer;
int type;
int index;
int channel;
int overlay;
struct regmap *regs;
struct drm_plane plane;
struct sun8i_mixer *mixer;
int type;
int index;
int channel;
int overlay;
struct regmap *regs;
const struct sun8i_layer_cfg *cfg;
};
static inline struct sun8i_layer *
@@ -260,14 +261,14 @@ sun8i_blender_regmap(struct sun8i_mixer *mixer)
}
static inline u32
sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
sun8i_channel_base(struct sun8i_layer *layer)
{
if (mixer->cfg->de_type == SUN8I_MIXER_DE33)
return DE33_CH_BASE + channel * DE33_CH_SIZE;
else if (mixer->cfg->de_type == SUN8I_MIXER_DE3)
return DE3_CH_BASE + channel * DE3_CH_SIZE;
if (layer->cfg->de_type == SUN8I_MIXER_DE33)
return DE33_CH_BASE + layer->channel * DE33_CH_SIZE;
else if (layer->cfg->de_type == SUN8I_MIXER_DE3)
return DE3_CH_BASE + layer->channel * DE3_CH_SIZE;
else
return DE2_CH_BASE + channel * DE2_CH_SIZE;
return DE2_CH_BASE + layer->channel * DE2_CH_SIZE;
}
int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format);

24
drivers/gpu/drm/sun4i/sun8i_ui_layer.c
View File

@@ -28,10 +28,9 @@
static void sun8i_ui_layer_disable(struct sun8i_layer *layer)
{
struct sun8i_mixer *mixer = layer->mixer;
u32 ch_base = sun8i_channel_base(mixer, layer->channel);
u32 ch_base = sun8i_channel_base(layer);
regmap_write(mixer->engine.regs,
regmap_write(layer->regs,
SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay), 0);
}
@@ -39,11 +38,10 @@ static void sun8i_ui_layer_update_attributes(struct sun8i_layer *layer,
struct drm_plane *plane)
{
struct drm_plane_state *state = plane->state;
struct sun8i_mixer *mixer = layer->mixer;
const struct drm_format_info *fmt;
u32 val, ch_base, hw_fmt;
ch_base = sun8i_channel_base(mixer, layer->channel);
ch_base = sun8i_channel_base(layer);
fmt = state->fb->format;
sun8i_mixer_drm_format_to_hw(fmt->format, &hw_fmt);
@@ -62,7 +60,6 @@ static void sun8i_ui_layer_update_coord(struct sun8i_layer *layer,
struct drm_plane *plane)
{
struct drm_plane_state *state = plane->state;
struct sun8i_mixer *mixer = layer->mixer;
u32 src_w, src_h, dst_w, dst_h;
u32 outsize, insize;
u32 hphase, vphase;
@@ -71,7 +68,7 @@ static void sun8i_ui_layer_update_coord(struct sun8i_layer *layer,
DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n",
layer->channel, layer->overlay);
ch_base = sun8i_channel_base(mixer, layer->channel);
ch_base = sun8i_channel_base(layer);
src_w = drm_rect_width(&state->src) >> 16;
src_h = drm_rect_height(&state->src) >> 16;
@@ -103,7 +100,7 @@ static void sun8i_ui_layer_update_coord(struct sun8i_layer *layer,
hscale = state->src_w / state->crtc_w;
vscale = state->src_h / state->crtc_h;
if (mixer->cfg->de_type == SUN8I_MIXER_DE33) {
if (layer->cfg->de_type == SUN8I_MIXER_DE33) {
sun8i_vi_scaler_setup(layer, src_w, src_h, dst_w, dst_h,
hscale, vscale, hphase, vphase,
state->fb->format);
@@ -115,7 +112,7 @@ static void sun8i_ui_layer_update_coord(struct sun8i_layer *layer,
}
} else {
DRM_DEBUG_DRIVER("HW scaling is not needed\n");
if (mixer->cfg->de_type == SUN8I_MIXER_DE33)
if (layer->cfg->de_type == SUN8I_MIXER_DE33)
sun8i_vi_scaler_enable(layer, false);
else
sun8i_ui_scaler_enable(layer, false);
@@ -126,14 +123,13 @@ static void sun8i_ui_layer_update_buffer(struct sun8i_layer *layer,
struct drm_plane *plane)
{
struct drm_plane_state *state = plane->state;
struct sun8i_mixer *mixer = layer->mixer;
struct drm_framebuffer *fb = state->fb;
struct drm_gem_dma_object *gem;
dma_addr_t dma_addr;
u32 ch_base;
int bpp;
ch_base = sun8i_channel_base(mixer, layer->channel);
ch_base = sun8i_channel_base(layer);
/* Get the physical address of the buffer in memory */
gem = drm_fb_dma_get_gem_obj(fb, 0);
@@ -190,7 +186,7 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
min_scale = DRM_PLANE_NO_SCALING;
max_scale = DRM_PLANE_NO_SCALING;
if (layer->mixer->cfg->lay_cfg.scaler_mask & BIT(layer->channel)) {
if (layer->cfg->scaler_mask & BIT(layer->channel)) {
min_scale = SUN8I_UI_SCALER_SCALE_MIN;
max_scale = SUN8I_UI_SCALER_SCALE_MAX;
}
@@ -266,7 +262,8 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
enum drm_plane_type type,
struct regmap *regs,
int index, int phy_index,
int plane_cnt)
int plane_cnt,
const struct sun8i_layer_cfg *cfg)
{
struct sun8i_layer *layer;
int ret;
@@ -281,6 +278,7 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
layer->channel = phy_index;
layer->overlay = 0;
layer->regs = regs;
layer->cfg = cfg;
/* possible crtcs are set later */
ret = drm_universal_plane_init(drm, &layer->plane, 0,

3
drivers/gpu/drm/sun4i/sun8i_ui_layer.h
View File

@@ -54,5 +54,6 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
enum drm_plane_type type,
struct regmap *regs,
int index, int phy_index,
int plane_cnt);
int plane_cnt,
const struct sun8i_layer_cfg *cfg);
#endif /* _SUN8I_UI_LAYER_H_ */

16
drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
View File

@@ -89,18 +89,18 @@ static const u32 lan2coefftab16[240] = {
0x0b1c1603, 0x0d1c1502, 0x0e1d1401, 0x0f1d1301,
};
static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel)
static u32 sun8i_ui_scaler_base(struct sun8i_layer *layer)
{
int offset = mixer->cfg->lay_cfg.vi_scaler_num;
int offset = layer->cfg->vi_scaler_num;
if (mixer->cfg->de_type == SUN8I_MIXER_DE3)
if (layer->cfg->de_type == SUN8I_MIXER_DE3)
return DE3_VI_SCALER_UNIT_BASE +
DE3_VI_SCALER_UNIT_SIZE * offset +
DE3_UI_SCALER_UNIT_SIZE * (channel - offset);
DE3_UI_SCALER_UNIT_SIZE * (layer->channel - offset);
else
return DE2_VI_SCALER_UNIT_BASE +
DE2_VI_SCALER_UNIT_SIZE * offset +
DE2_UI_SCALER_UNIT_SIZE * (channel - offset);
DE2_UI_SCALER_UNIT_SIZE * (layer->channel - offset);
}
static int sun8i_ui_scaler_coef_index(unsigned int step)
@@ -129,10 +129,9 @@ static int sun8i_ui_scaler_coef_index(unsigned int step)
void sun8i_ui_scaler_enable(struct sun8i_layer *layer, bool enable)
{
struct sun8i_mixer *mixer = layer->mixer;
u32 val, base;
base = sun8i_ui_scaler_base(mixer, layer->channel);
base = sun8i_ui_scaler_base(layer);
if (enable)
val = SUN8I_SCALER_GSU_CTRL_EN |
@@ -147,12 +146,11 @@ void sun8i_ui_scaler_setup(struct sun8i_layer *layer,
u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
u32 hscale, u32 vscale, u32 hphase, u32 vphase)
{
struct sun8i_mixer *mixer = layer->mixer;
u32 insize, outsize;
int i, offset;
u32 base;
base = sun8i_ui_scaler_base(mixer, layer->channel);
base = sun8i_ui_scaler_base(layer);
hphase <<= SUN8I_UI_SCALER_PHASE_FRAC - 16;
vphase <<= SUN8I_UI_SCALER_PHASE_FRAC - 16;

31
drivers/gpu/drm/sun4i/sun8i_vi_layer.c
View File

@@ -21,10 +21,9 @@
static void sun8i_vi_layer_disable(struct sun8i_layer *layer)
{
struct sun8i_mixer *mixer = layer->mixer;
u32 ch_base = sun8i_channel_base(mixer, layer->channel);
u32 ch_base = sun8i_channel_base(layer);
regmap_write(mixer->engine.regs,
regmap_write(layer->regs,
SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), 0);
}
@@ -32,11 +31,10 @@ static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer,
struct drm_plane *plane)
{
struct drm_plane_state *state = plane->state;
struct sun8i_mixer *mixer = layer->mixer;
const struct drm_format_info *fmt;
u32 val, ch_base, hw_fmt;
ch_base = sun8i_channel_base(mixer, layer->channel);
ch_base = sun8i_channel_base(layer);
fmt = state->fb->format;
sun8i_mixer_drm_format_to_hw(fmt->format, &hw_fmt);
@@ -44,7 +42,7 @@ static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer,
if (!fmt->is_yuv)
val |= SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;
val |= SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
if (layer->cfg->de_type >= SUN8I_MIXER_DE3) {
val |= SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA(state->alpha >> 8);
val |= (state->alpha == DRM_BLEND_ALPHA_OPAQUE) ?
SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL :
@@ -54,7 +52,7 @@ static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer,
regmap_write(layer->regs,
SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val);
if (mixer->cfg->lay_cfg.de2_fcc_alpha) {
if (layer->cfg->de2_fcc_alpha) {
regmap_write(layer->regs,
SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG,
SUN8I_MIXER_FCC_GLOBAL_ALPHA(state->alpha >> 8));
@@ -78,7 +76,7 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer,
DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n",
layer->channel, layer->overlay);
ch_base = sun8i_channel_base(mixer, layer->channel);
ch_base = sun8i_channel_base(layer);
src_w = drm_rect_width(&state->src) >> 16;
src_h = drm_rect_height(&state->src) >> 16;
@@ -153,7 +151,7 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer,
}
/* it seems that every RGB scaler has buffer for 2048 pixels */
scanline = subsampled ? mixer->cfg->lay_cfg.scanline_yuv : 2048;
scanline = subsampled ? layer->cfg->scanline_yuv : 2048;
if (src_w > scanline) {
DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n");
@@ -195,7 +193,6 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer,
struct drm_plane *plane)
{
struct drm_plane_state *state = plane->state;
struct sun8i_mixer *mixer = layer->mixer;
struct drm_framebuffer *fb = state->fb;
const struct drm_format_info *format = fb->format;
struct drm_gem_dma_object *gem;
@@ -204,7 +201,7 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer,
u32 ch_base;
int i;
ch_base = sun8i_channel_base(mixer, layer->channel);
ch_base = sun8i_channel_base(layer);
/* Adjust x and y to be dividable by subsampling factor */
src_x = (state->src.x1 >> 16) & ~(format->hsub - 1);
@@ -278,7 +275,7 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
min_scale = DRM_PLANE_NO_SCALING;
max_scale = DRM_PLANE_NO_SCALING;
if (layer->mixer->cfg->lay_cfg.scaler_mask & BIT(layer->channel)) {
if (layer->cfg->scaler_mask & BIT(layer->channel)) {
min_scale = SUN8I_VI_SCALER_SCALE_MIN;
max_scale = SUN8I_VI_SCALER_SCALE_MAX;
}
@@ -414,7 +411,8 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
enum drm_plane_type type,
struct regmap *regs,
int index, int phy_index,
int plane_cnt)
int plane_cnt,
const struct sun8i_layer_cfg *cfg)
{
u32 supported_encodings, supported_ranges;
unsigned int format_count;
@@ -432,8 +430,9 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
layer->channel = phy_index;
layer->overlay = 0;
layer->regs = regs;
layer->cfg = cfg;
if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
if (layer->cfg->de_type >= SUN8I_MIXER_DE3) {
formats = sun8i_vi_layer_de3_formats;
format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
} else {
@@ -452,7 +451,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
return ERR_PTR(ret);
}
if (mixer->cfg->lay_cfg.de2_fcc_alpha || mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
if (layer->cfg->de2_fcc_alpha || layer->cfg->de_type >= SUN8I_MIXER_DE3) {
ret = drm_plane_create_alpha_property(&layer->plane);
if (ret) {
dev_err(drm->dev, "Couldn't add alpha property\n");
@@ -469,7 +468,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) |
BIT(DRM_COLOR_YCBCR_BT709);
if (mixer->cfg->de_type >= SUN8I_MIXER_DE3)
if (layer->cfg->de_type >= SUN8I_MIXER_DE3)
supported_encodings |= BIT(DRM_COLOR_YCBCR_BT2020);
supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |

3
drivers/gpu/drm/sun4i/sun8i_vi_layer.h
View File

@@ -59,5 +59,6 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
enum drm_plane_type type,
struct regmap *regs,
int index, int phy_index,
int plane_cnt);
int plane_cnt,
const struct sun8i_layer_cfg *cfg);
#endif /* _SUN8I_VI_LAYER_H_ */

19
drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
View File

@@ -833,17 +833,17 @@ static const u32 bicubic4coefftab32[480] = {
0x1012110d, 0x1012110d, 0x1013110c, 0x1013110c,
};
static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
static u32 sun8i_vi_scaler_base(struct sun8i_layer *layer)
{
if (mixer->cfg->de_type == SUN8I_MIXER_DE33)
if (layer->cfg->de_type == SUN8I_MIXER_DE33)
return DE33_VI_SCALER_UNIT_BASE +
DE33_CH_SIZE * channel;
else if (mixer->cfg->de_type == SUN8I_MIXER_DE3)
DE33_CH_SIZE * layer->channel;
else if (layer->cfg->de_type == SUN8I_MIXER_DE3)
return DE3_VI_SCALER_UNIT_BASE +
DE3_VI_SCALER_UNIT_SIZE * channel;
DE3_VI_SCALER_UNIT_SIZE * layer->channel;
else
return DE2_VI_SCALER_UNIT_BASE +
DE2_VI_SCALER_UNIT_SIZE * channel;
DE2_VI_SCALER_UNIT_SIZE * layer->channel;
}
static int sun8i_vi_scaler_coef_index(unsigned int step)
@@ -914,7 +914,7 @@ void sun8i_vi_scaler_enable(struct sun8i_layer *layer, bool enable)
{
u32 val, base;
base = sun8i_vi_scaler_base(layer->mixer, layer->channel);
base = sun8i_vi_scaler_base(layer);
if (enable)
val = SUN8I_SCALER_VSU_CTRL_EN |
@@ -931,12 +931,11 @@ void sun8i_vi_scaler_setup(struct sun8i_layer *layer,
u32 hscale, u32 vscale, u32 hphase, u32 vphase,
const struct drm_format_info *format)
{
struct sun8i_mixer *mixer = layer->mixer;
u32 chphase, cvphase;
u32 insize, outsize;
u32 base;
base = sun8i_vi_scaler_base(mixer, layer->channel);
base = sun8i_vi_scaler_base(layer);
hphase <<= SUN8I_VI_SCALER_PHASE_FRAC - 16;
vphase <<= SUN8I_VI_SCALER_PHASE_FRAC - 16;
@@ -960,7 +959,7 @@ void sun8i_vi_scaler_setup(struct sun8i_layer *layer,
cvphase = vphase;
}
if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
if (layer->cfg->de_type >= SUN8I_MIXER_DE3) {
u32 val;
if (format->hsub == 1 && format->vsub == 1)