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Code

pinctrl: aspeed-g6: Add PCIe RC PERST pin group

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The PCIe RC PERST uses SSPRST# as PERST#  and enable this pin
to output.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20250715034320.2553837-8-jacky_chou@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Jacky Chou 2025-07-15 11:43:17 +08:00 committed by Linus Walleij
parent 0bbd90c2c6
commit b1d4c90bff
1 changed files with 11 additions and 1 deletions
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12
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
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@ -17,6 +17,7 @@
#include "../pinctrl-utils.h"
#include "pinctrl-aspeed.h"
#define SCU040 0x040 /* Reset Control Set 1 */
#define SCU400 0x400 /* Multi-function Pin Control #1 */
#define SCU404 0x404 /* Multi-function Pin Control #2 */
#define SCU40C 0x40C /* Multi-function Pin Control #3 */
@ -52,7 +53,7 @@
#define SCU6D0 0x6D0 /* Multi-function Pin Control #29 */
#define SCUC20 0xC20 /* PCIE configuration Setting Control */
#define ASPEED_G6_NR_PINS 256
#define ASPEED_G6_NR_PINS 258
#define M24 0
SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0));
@ -1636,6 +1637,12 @@ FUNC_DECL_1(USB11BHID, USBB);
FUNC_DECL_1(USB2BD, USBB);
FUNC_DECL_1(USB2BH, USBB);
#define D7 257
SIG_EXPR_LIST_DECL_SESG(D7, RCRST, PCIERC1, SIG_DESC_SET(SCU040, 19),
SIG_DESC_SET(SCU500, 24));
PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, RCRST));
FUNC_GROUP_DECL(PCIERC1, D7);
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
@ -1806,6 +1813,7 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
ASPEED_PINCTRL_PIN(D4),
ASPEED_PINCTRL_PIN(D5),
ASPEED_PINCTRL_PIN(D6),
ASPEED_PINCTRL_PIN(D7),
ASPEED_PINCTRL_PIN(E1),
ASPEED_PINCTRL_PIN(E11),
ASPEED_PINCTRL_PIN(E12),
@ -2073,6 +2081,7 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = {
ASPEED_PINCTRL_GROUP(SALT9G1),
ASPEED_PINCTRL_GROUP(SD1),
ASPEED_PINCTRL_GROUP(SD2),
ASPEED_PINCTRL_GROUP(PCIERC1),
ASPEED_PINCTRL_GROUP(EMMCG1),
ASPEED_PINCTRL_GROUP(EMMCG4),
ASPEED_PINCTRL_GROUP(EMMCG8),
@ -2314,6 +2323,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
ASPEED_PINCTRL_FUNC(SPI2),
ASPEED_PINCTRL_FUNC(SPI2CS1),
ASPEED_PINCTRL_FUNC(SPI2CS2),
ASPEED_PINCTRL_FUNC(PCIERC1),
ASPEED_PINCTRL_FUNC(TACH0),
ASPEED_PINCTRL_FUNC(TACH1),
ASPEED_PINCTRL_FUNC(TACH10),