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drm/amdgpu: Add mqd for userq compute queue

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Add mqd for userq compute queue for gfx11/gfx12

Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Arunpravin Paneer Selvam
2024-12-09 19:20:56 +05:30
committed by Alex Deucher
parent 31f7efcdca
commit 9ed335d939
4 changed files with 12 additions and 4 deletions
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4
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
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@@ -4312,6 +4312,10 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
mqd->cp_hqd_active = prop->hqd_active;
/* set UQ fenceaddress */
mqd->fence_address_lo = lower_32_bits(prop->fence_address);
mqd->fence_address_hi = upper_32_bits(prop->fence_address);
return 0;
}

4
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
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@@ -3215,6 +3215,10 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
mqd->cp_hqd_active = prop->hqd_active;
/* set UQ fenceaddress */
mqd->fence_address_lo = lower_32_bits(prop->fence_address);
mqd->fence_address_hi = upper_32_bits(prop->fence_address);
return 0;
}

4
drivers/gpu/drm/amd/include/v11_structs.h
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@@ -1118,8 +1118,8 @@ struct v11_compute_mqd {
uint32_t reserved_443; // offset: 443 (0x1BB)
uint32_t reserved_444; // offset: 444 (0x1BC)
uint32_t reserved_445; // offset: 445 (0x1BD)
uint32_t reserved_446; // offset: 446 (0x1BE)
uint32_t reserved_447; // offset: 447 (0x1BF)
uint32_t fence_address_lo; // offset: 446 (0x1BE)
uint32_t fence_address_hi; // offset: 447 (0x1BF)
uint32_t gws_0_val; // offset: 448 (0x1C0)
uint32_t gws_1_val; // offset: 449 (0x1C1)
uint32_t gws_2_val; // offset: 450 (0x1C2)

4
drivers/gpu/drm/amd/include/v12_structs.h
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@@ -1118,8 +1118,8 @@ struct v12_compute_mqd {
uint32_t reserved_443; // offset: 443 (0x1BB)
uint32_t reserved_444; // offset: 444 (0x1BC)
uint32_t reserved_445; // offset: 445 (0x1BD)
uint32_t reserved_446; // offset: 446 (0x1BE)
uint32_t reserved_447; // offset: 447 (0x1BF)
uint32_t fence_address_lo; // offset: 446 (0x1BE)
uint32_t fence_address_hi; // offset: 447 (0x1BF)
uint32_t gws_0_val; // offset: 448 (0x1C0)
uint32_t gws_1_val; // offset: 449 (0x1C1)
uint32_t gws_2_val; // offset: 450 (0x1C2)