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Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf

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Cross merge bpf/master after 6.17-rc1.

No conflict.

Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
This commit is contained in:
Martin KaFai Lau
2025-08-11 16:15:41 -07:00
parent fa47913284 8f5ae30d69
commit 9e293d47bf
1195 changed files with 33452 additions and 11564 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
.mailmap
View File

@@ -673,6 +673,7 @@ Muchun Song <muchun.song@linux.dev> <smuchun@gmail.com>
Ross Zwisler <zwisler@kernel.org> <ross.zwisler@linux.intel.com>
Rudolf Marek <R.Marek@sh.cvut.cz>
Rui Saraiva <rmps@joel.ist.utl.pt>
Sachin Mokashi <sachin.mokashi@intel.com> <sachinx.mokashi@intel.com>
Sachin P Sant <ssant@in.ibm.com>
Sai Prakash Ranjan <quic_saipraka@quicinc.com> <saiprakash.ranjan@codeaurora.org>
Sakari Ailus <sakari.ailus@linux.intel.com> <sakari.ailus@iki.fi>

6
CREDITS
View File

@@ -4378,6 +4378,12 @@ S: 542 West 112th Street, 5N
S: New York, New York 10025
S: USA
N: Masahiro Yamada
E: masahiroy@kernel.org
D: Kbuild Maintainer 2017-2025
D: Kconfig Maintainer 2018-2025
S: Japan
N: Li Yang
E: leoli@freescale.com
D: Freescale Highspeed USB device driver

7
Documentation/ABI/testing/sysfs-firmware-efi
View File

@@ -36,3 +36,10 @@ Description: Displays the content of the Runtime Configuration Interface
Table version 2 on Dell EMC PowerEdge systems in binary format
Users: It is used by Dell EMC OpenManage Server Administrator tool to
populate BIOS setup page.
What: /sys/firmware/efi/ovmf_debug_log
Date: July 2025
Contact: Gerd Hoffmann <kraxel@redhat.com>, linux-efi@vger.kernel.org
Description: Displays the content of the OVMF debug log buffer. The file is
only present in case the firmware supports logging to a memory
buffer.

22
Documentation/ABI/testing/sysfs-fs-f2fs
View File

@@ -861,3 +861,25 @@ Description: This is a read-only entry to show the value of sb.s_encoding_flags,
SB_ENC_STRICT_MODE_FL 0x00000001
SB_ENC_NO_COMPAT_FALLBACK_FL 0x00000002
============================ ==========
What: /sys/fs/f2fs/<disk>/reserved_pin_section
Date: June 2025
Contact: "Chao Yu" <chao@kernel.org>
Description: This threshold is used to control triggering garbage collection while
fallocating on pinned file, so, it can guarantee there is enough free
reserved section before preallocating on pinned file.
By default, the value is ovp_sections, especially, for zoned ufs, the
value is 1.
What: /sys/fs/f2fs/<disk>/gc_boost_gc_multiple
Date: June 2025
Contact: "Daeho Jeong" <daehojeong@google.com>
Description: Set a multiplier for the background GC migration window when F2FS GC is
boosted. The range should be from 1 to the segment count in a section.
Default: 5
What: /sys/fs/f2fs/<disk>/gc_boost_gc_greedy
Date: June 2025
Contact: "Daeho Jeong" <daehojeong@google.com>
Description: Control GC algorithm for boost GC. 0: cost benefit, 1: greedy
Default: 1

56
Documentation/accounting/delay-accounting.rst
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@@ -131,3 +131,59 @@ Get IO accounting for pid 1, it works only with -p::
linuxrc: read=65536, write=0, cancelled_write=0
The above command can be used with -v to get more debug information.
After the system starts, use `delaytop` to get the system-wide delay information,
which includes system-wide PSI information and Top-N high-latency tasks.
`delaytop` supports sorting by CPU latency in descending order by default,
displays the top 20 high-latency tasks by default, and refreshes the latency
data every 2 seconds by default.
Get PSI information and Top-N tasks delay, since system boot::
bash# ./delaytop
System Pressure Information: (avg10/avg60/avg300/total)
CPU some: 0.0%/ 0.0%/ 0.0%/ 345(ms)
CPU full: 0.0%/ 0.0%/ 0.0%/ 0(ms)
Memory full: 0.0%/ 0.0%/ 0.0%/ 0(ms)
Memory some: 0.0%/ 0.0%/ 0.0%/ 0(ms)
IO full: 0.0%/ 0.0%/ 0.0%/ 65(ms)
IO some: 0.0%/ 0.0%/ 0.0%/ 79(ms)
IRQ full: 0.0%/ 0.0%/ 0.0%/ 0(ms)
Top 20 processes (sorted by CPU delay):
PID TGID COMMAND CPU(ms) IO(ms) SWAP(ms) RCL(ms) THR(ms) CMP(ms) WP(ms) IRQ(ms)
----------------------------------------------------------------------------------------------
161 161 zombie_memcg_re 1.40 0.00 0.00 0.00 0.00 0.00 0.00 0.00
130 130 blkcg_punt_bio 1.37 0.00 0.00 0.00 0.00 0.00 0.00 0.00
444 444 scsi_tmf_0 0.73 0.00 0.00 0.00 0.00 0.00 0.00 0.00
1280 1280 rsyslogd 0.53 0.04 0.00 0.00 0.00 0.00 0.00 0.00
12 12 ksoftirqd/0 0.47 0.00 0.00 0.00 0.00 0.00 0.00 0.00
1277 1277 nbd-server 0.44 0.00 0.00 0.00 0.00 0.00 0.00 0.00
308 308 kworker/2:2-sys 0.41 0.00 0.00 0.00 0.00 0.00 0.00 0.00
55 55 netns 0.36 0.00 0.00 0.00 0.00 0.00 0.00 0.00
1187 1187 acpid 0.31 0.03 0.00 0.00 0.00 0.00 0.00 0.00
6184 6184 kworker/1:2-sys 0.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00
186 186 kaluad 0.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00
18 18 ksoftirqd/1 0.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00
185 185 kmpath_rdacd 0.23 0.00 0.00 0.00 0.00 0.00 0.00 0.00
190 190 kstrp 0.23 0.00 0.00 0.00 0.00 0.00 0.00 0.00
2759 2759 agetty 0.20 0.03 0.00 0.00 0.00 0.00 0.00 0.00
1190 1190 kworker/0:3-sys 0.19 0.00 0.00 0.00 0.00 0.00 0.00 0.00
1272 1272 sshd 0.15 0.04 0.00 0.00 0.00 0.00 0.00 0.00
1156 1156 license 0.15 0.11 0.00 0.00 0.00 0.00 0.00 0.00
134 134 md 0.13 0.00 0.00 0.00 0.00 0.00 0.00 0.00
6142 6142 kworker/3:2-xfs 0.13 0.00 0.00 0.00 0.00 0.00 0.00 0.00
Dynamic interactive interface of delaytop::
# ./delaytop -p pid
Print delayacct stats
# ./delaytop -P num
Display the top N tasks
# ./delaytop -n num
Set delaytop refresh frequency (num times)
# ./delaytop -d secs
Specify refresh interval as secs

16
Documentation/admin-guide/device-mapper/thin-provisioning.rst
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@@ -80,11 +80,11 @@ less sharing than average you'll need a larger-than-average metadata device.
As a guide, we suggest you calculate the number of bytes to use in the
metadata device as 48 * $data_dev_size / $data_block_size but round it up
to 2MB if the answer is smaller. If you're creating large numbers of
to 2MiB if the answer is smaller. If you're creating large numbers of
snapshots which are recording large amounts of change, you may find you
need to increase this.
The largest size supported is 16GB: If the device is larger,
The largest size supported is 16GiB: If the device is larger,
a warning will be issued and the excess space will not be used.
Reloading a pool table
@@ -107,13 +107,13 @@ Using an existing pool device
$data_block_size gives the smallest unit of disk space that can be
allocated at a time expressed in units of 512-byte sectors.
$data_block_size must be between 128 (64KB) and 2097152 (1GB) and a
multiple of 128 (64KB). $data_block_size cannot be changed after the
$data_block_size must be between 128 (64KiB) and 2097152 (1GiB) and a
multiple of 128 (64KiB). $data_block_size cannot be changed after the
thin-pool is created. People primarily interested in thin provisioning
may want to use a value such as 1024 (512KB). People doing lots of
snapshotting may want a smaller value such as 128 (64KB). If you are
may want to use a value such as 1024 (512KiB). People doing lots of
snapshotting may want a smaller value such as 128 (64KiB). If you are
not zeroing newly-allocated data, a larger $data_block_size in the
region of 256000 (128MB) is suggested.
region of 262144 (128MiB) is suggested.
$low_water_mark is expressed in blocks of size $data_block_size. If
free space on the data device drops below this level then a dm event
@@ -291,7 +291,7 @@ i) Constructor
error_if_no_space:
Error IOs, instead of queueing, if no space.
Data block size must be between 64KB (128 sectors) and 1GB
Data block size must be between 64KiB (128 sectors) and 1GiB
(2097152 sectors) inclusive.

21
Documentation/admin-guide/kdump/kdump.rst
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@@ -311,6 +311,27 @@ crashkernel syntax
crashkernel=0,low
4) crashkernel=size,cma
Reserve additional crash kernel memory from CMA. This reservation is
usable by the first system's userspace memory and kernel movable
allocations (memory balloon, zswap). Pages allocated from this memory
range will not be included in the vmcore so this should not be used if
dumping of userspace memory is intended and it has to be expected that
some movable kernel pages may be missing from the dump.
A standard crashkernel reservation, as described above, is still needed
to hold the crash kernel and initrd.
This option increases the risk of a kdump failure: DMA transfers
configured by the first kernel may end up corrupting the second
kernel's memory.
This reservation method is intended for systems that can't afford to
sacrifice enough memory for standard crashkernel reservation and where
less reliable and possibly incomplete kdump is preferable to no kdump at
all.
Boot into System Kernel
-----------------------
1) Update the boot loader (such as grub, yaboot, or lilo) configuration

86
Documentation/admin-guide/kernel-parameters.txt
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@@ -994,6 +994,28 @@
0: to disable low allocation.
It will be ignored when crashkernel=X,high is not used
or memory reserved is below 4G.
crashkernel=size[KMG],cma
[KNL, X86] Reserve additional crash kernel memory from
CMA. This reservation is usable by the first system's
userspace memory and kernel movable allocations (memory
balloon, zswap). Pages allocated from this memory range
will not be included in the vmcore so this should not
be used if dumping of userspace memory is intended and
it has to be expected that some movable kernel pages
may be missing from the dump.
A standard crashkernel reservation, as described above,
is still needed to hold the crash kernel and initrd.
This option increases the risk of a kdump failure: DMA
transfers configured by the first kernel may end up
corrupting the second kernel's memory.
This reservation method is intended for systems that
can't afford to sacrifice enough memory for standard
crashkernel reservation and where less reliable and
possibly incomplete kdump is preferable to no kdump at
all.
cryptomgr.notests
[KNL] Disable crypto self-tests
@@ -1806,6 +1828,27 @@
backtraces on all cpus.
Format: 0 | 1
hash_pointers=
[KNL,EARLY]
By default, when pointers are printed to the console
or buffers via the %p format string, that pointer is
"hashed", i.e. obscured by hashing the pointer value.
This is a security feature that hides actual kernel
addresses from unprivileged users, but it also makes
debugging the kernel more difficult since unequal
pointers can no longer be compared. The choices are:
Format: { auto | always | never }
Default: auto
auto - Hash pointers unless slab_debug is enabled.
always - Always hash pointers (even if slab_debug is
enabled).
never - Never hash pointers. This option should only
be specified when debugging the kernel. Do
not use on production kernels. The boot
param "no_hash_pointers" is an alias for
this mode.
hashdist= [KNL,NUMA] Large hashes allocated during boot
are distributed across NUMA nodes. Defaults on
for 64-bit NUMA, off otherwise.
@@ -4194,18 +4237,7 @@
no_hash_pointers
[KNL,EARLY]
Force pointers printed to the console or buffers to be
unhashed. By default, when a pointer is printed via %p
format string, that pointer is "hashed", i.e. obscured
by hashing the pointer value. This is a security feature
that hides actual kernel addresses from unprivileged
users, but it also makes debugging the kernel more
difficult since unequal pointers can no longer be
compared. However, if this command-line option is
specified, then all normal pointers will have their true
value printed. This option should only be specified when
debugging the kernel. Please do not use on production
kernels.
Alias for "hash_pointers=never".
nohibernate [HIBERNATION] Disable hibernation and resume.
@@ -4557,7 +4589,7 @@
bit 2: print timer info
bit 3: print locks info if CONFIG_LOCKDEP is on
bit 4: print ftrace buffer
bit 5: print all printk messages in buffer
bit 5: replay all messages on consoles at the end of panic
bit 6: print all CPUs backtrace (if available in the arch)
bit 7: print only tasks in uninterruptible (blocked) state
*Be aware* that this option may print a _lot_ of lines,
@@ -4565,6 +4597,25 @@
Use this option carefully, maybe worth to setup a
bigger log buffer with "log_buf_len" along with this.
panic_sys_info= A comma separated list of extra information to be dumped
on panic.
Format: val[,val...]
Where @val can be any of the following:
tasks: print all tasks info
mem: print system memory info
timers: print timers info
locks: print locks info if CONFIG_LOCKDEP is on
ftrace: print ftrace buffer
all_bt: print all CPUs backtrace (if available in the arch)
blocked_tasks: print only tasks in uninterruptible (blocked) state
This is a human readable alternative to the 'panic_print' option.
panic_console_replay
When panic happens, replay all kernel messages on
consoles at the end of panic.
parkbd.port= [HW] Parallel port number the keyboard adapter is
connected to, default is 0.
Format: <parport#>
@@ -6603,6 +6654,10 @@
Documentation/admin-guide/mm/slab.rst.
(slub_debug legacy name also accepted for now)
Using this option implies the "no_hash_pointers"
option which can be undone by adding the
"hash_pointers=always" option.
slab_max_order= [MM]
Determines the maximum allowed order for slabs.
A high setting may cause OOMs due to memory
@@ -7032,6 +7087,11 @@
consumed by the stack hash table. By default this is set
to false.
stack_depot_max_pools= [KNL,EARLY]
Specify the maximum number of pools to use for storing
stack traces. Pools are allocated on-demand up to this
limit. Default value is 8191 pools.
stacktrace [FTRACE]
Enabled the stack tracer on boot up.

20
Documentation/admin-guide/sysctl/kernel.rst
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@@ -890,7 +890,7 @@ bit 1 print system memory info
bit 2 print timer info
bit 3 print locks info if ``CONFIG_LOCKDEP`` is on
bit 4 print ftrace buffer
bit 5 print all printk messages in buffer
bit 5 replay all messages on consoles at the end of panic
bit 6 print all CPUs backtrace (if available in the arch)
bit 7 print only tasks in uninterruptible (blocked) state
===== ============================================
@@ -900,6 +900,24 @@ So for example to print tasks and memory info on panic, user can::
echo 3 > /proc/sys/kernel/panic_print
panic_sys_info
==============
A comma separated list of extra information to be dumped on panic,
for example, "tasks,mem,timers,...". It is a human readable alternative
to 'panic_print'. Possible values are:
============= ===================================================
tasks print all tasks info
mem print system memory info
timer print timers info
lock print locks info if CONFIG_LOCKDEP is on
ftrace print ftrace buffer
all_bt print all CPUs backtrace (if available in the arch)
blocked_tasks print only tasks in uninterruptible (blocked) state
============= ===================================================
panic_on_rcu_stall
==================

1
Documentation/core-api/mm-api.rst
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@@ -133,4 +133,3 @@ More Memory Management Functions
.. kernel-doc:: mm/mmu_notifier.c
.. kernel-doc:: mm/balloon_compaction.c
.. kernel-doc:: mm/huge_memory.c
.. kernel-doc:: mm/io-mapping.c

5
Documentation/devicetree/bindings/i2c/apple,i2c.yaml
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@@ -22,6 +22,11 @@ properties:
compatible:
items:
- enum:
- apple,s5l8960x-i2c
- apple,t7000-i2c
- apple,s8000-i2c
- apple,t8010-i2c
- apple,t8015-i2c
- apple,t8103-i2c
- apple,t8112-i2c
- apple,t6000-i2c

179
Documentation/devicetree/bindings/i3c/renesas,i3c.yaml Normal file
View File

@@ -0,0 +1,179 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/G3S and RZ/G3E I3C Bus Interface
maintainers:
- Wolfram Sang <wsa+renesas@sang-engineering.com>
- Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
properties:
compatible:
items:
- enum:
- renesas,r9a08g045-i3c # RZ/G3S
- renesas,r9a09g047-i3c # RZ/G3E
reg:
maxItems: 1
interrupts:
items:
- description: Non-recoverable internal error interrupt
- description: Normal transfer error interrupt
- description: Normal transfer abort interrupt
- description: Normal response status buffer full interrupt
- description: Normal command buffer empty interrupt
- description: Normal IBI status buffer full interrupt
- description: Normal Rx data buffer full interrupt
- description: Normal Tx data buffer empty interrupt
- description: Normal receive status buffer full interrupt
- description: START condition detection interrupt
- description: STOP condition detection interrupt
- description: Transmit end interrupt
- description: NACK detection interrupt
- description: Arbitration lost interrupt
- description: Timeout detection interrupt
- description: Wake-up condition detection interrupt
- description: HDR Exit Pattern detection interrupt
minItems: 16
interrupt-names:
items:
- const: ierr
- const: terr
- const: abort
- const: resp
- const: cmd
- const: ibi
- const: rx
- const: tx
- const: rcv
- const: st
- const: sp
- const: tend
- const: nack
- const: al
- const: tmo
- const: wu
- const: exit
minItems: 16
clocks:
items:
- description: APB bus clock
- description: transfer clock
- description: SFRs clock
minItems: 2
clock-names:
items:
- const: pclk
- const: tclk
- const: pclkrw
minItems: 2
power-domains:
maxItems: 1
resets:
items:
- description: Reset signal
- description: APB interface reset signal/SCAN reset signal
reset-names:
items:
- const: presetn
- const: tresetn
required:
- compatible
- reg
- interrupts
- interrupt-names
- clock-names
- clocks
- power-domains
- resets
- reset-names
allOf:
- $ref: i3c.yaml#
- if:
properties:
compatible:
contains:
const: renesas,r9a08g045-i3c
then:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
interrupts:
minItems: 17
interrupt-names:
minItems: 17
- if:
properties:
compatible:
contains:
const: renesas,r9a09g047-i3c
then:
properties:
clocks:
minItems: 3
clock-names:
minItems: 3
interrupts:
maxItems: 16
interrupt-names:
maxItems: 16
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r9a08g045-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i3c@1005b000 {
compatible = "renesas,r9a08g045-i3c";
reg = <0x1005b000 0x1000>;
clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
<&cpg CPG_MOD R9A08G045_I3C_TCLK>;
clock-names = "pclk", "tclk";
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ierr", "terr", "abort", "resp",
"cmd", "ibi", "rx", "tx", "rcv",
"st", "sp", "tend", "nack",
"al", "tmo", "wu", "exit";
resets = <&cpg R9A08G045_I3C_PRESETN>,
<&cpg R9A08G045_I3C_TRESETN>;
reset-names = "presetn", "tresetn";
power-domains = <&cpg>;
#address-cells = <3>;
#size-cells = <0>;
};
...

20
Documentation/devicetree/bindings/input/syna,rmi4.yaml
View File

@@ -89,6 +89,24 @@ properties:
required:
- reg
rmi4-f1a@1a:
type: object
additionalProperties: false
$ref: input.yaml#
description:
RMI4 Function 1A is for capacitive keys.
properties:
reg:
maxItems: 1
linux,keycodes:
minItems: 1
maxItems: 4
required:
- reg
patternProperties:
"^rmi4-f1[12]@1[12]$":
type: object
@@ -201,6 +219,7 @@ allOf:
examples:
- |
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
@@ -234,6 +253,7 @@ examples:
rmi4-f1a@1a {
reg = <0x1a>;
linux,keycodes = <KEY_BACK KEY_HOME KEY_MENU>;
};
};
};

1
Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
View File

@@ -43,6 +43,7 @@ properties:
- focaltech,ft5452
- focaltech,ft6236
- focaltech,ft8201
- focaltech,ft8716
- focaltech,ft8719
reg:

16
Documentation/devicetree/bindings/input/touchscreen/lpc32xx-tsc.txt
View File

@@ -1,16 +0,0 @@
* NXP LPC32xx SoC Touchscreen Controller (TSC)
Required properties:
- compatible: must be "nxp,lpc3220-tsc"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The TSC/ADC interrupt
Example:
tsc@40048000 {
compatible = "nxp,lpc3220-tsc";
reg = <0x40048000 0x1000>;
interrupt-parent = <&mic>;
interrupts = <39 0>;
};

43
Documentation/devicetree/bindings/input/touchscreen/nxp,lpc3220-tsc.yaml Normal file
View File

@@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/nxp,lpc3220-tsc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC32xx SoC Touchscreen Controller (TSC)
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: nxp,lpc3220-tsc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/lpc32xx-clock.h>
touchscreen@40048000 {
compatible = "nxp,lpc3220-tsc";
reg = <0x40048000 0x1000>;
interrupt-parent = <&mic>;
interrupts = <39 0>;
clocks = <&clk LPC32XX_CLK_ADC>;
};

29
Documentation/devicetree/bindings/input/touchscreen/sitronix,st1232.yaml
View File

@@ -37,6 +37,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/input/linux-event-codes.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -46,5 +47,33 @@ examples:
reg = <0x55>;
interrupts = <2 0>;
gpios = <&gpio1 166 0>;
touch-overlay {
segment-0 {
label = "Touchscreen";
x-origin = <0>;
x-size = <240>;
y-origin = <40>;
y-size = <280>;
};
segment-1a {
label = "Camera light";
linux,code = <KEY_LIGHTS_TOGGLE>;
x-origin = <40>;
x-size = <40>;
y-origin = <0>;
y-size = <40>;
};
segment-2a {
label = "Power";
linux,code = <KEY_POWER>;
x-origin = <160>;
x-size = <40>;
y-origin = <0>;
y-size = <40>;
};
};
};
};

75
Documentation/devicetree/bindings/input/touchscreen/ti.tsc2007.yaml Normal file
View File

@@ -0,0 +1,75 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/ti.tsc2007.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments tsc2007 touchscreen controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: ti,tsc2007
reg:
maxItems: 1
interrupts:
maxItems: 1
ti,x-plate-ohms:
description: X-plate resistance in ohms.
gpios: true
pendown-gpio: true
ti,max-rt:
$ref: /schemas/types.yaml#/definitions/uint32
description: maximum pressure.
ti,fuzzx:
$ref: /schemas/types.yaml#/definitions/uint32
description:
specifies the absolute input fuzz x value.
If set, it will permit noise in the data up to +- the value given to the fuzz
parameter, that is used to filter noise from the event stream.
ti,fuzzy:
$ref: /schemas/types.yaml#/definitions/uint32
description: specifies the absolute input fuzz y value.
ti,fuzzz:
$ref: /schemas/types.yaml#/definitions/uint32
description: specifies the absolute input fuzz z value.
ti,poll-period:
$ref: /schemas/types.yaml#/definitions/uint32
description:
how much time to wait (in milliseconds) before reading again the
values from the tsc2007.
required:
- compatible
- reg
- ti,x-plate-ohms
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
touch@49 {
compatible = "ti,tsc2007";
reg = <0x49>;
interrupt-parent = <&gpio4>;
interrupts = <0x0 0x8>;
gpios = <&gpio4 0 0>;
ti,x-plate-ohms = <180>;
};
};

119
Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml
View File

@@ -87,6 +87,125 @@ properties:
touchscreen-y-plate-ohms:
description: Resistance of the Y-plate in Ohms
touch-overlay:
description: |
List of nodes defining segments (touch areas) on the touchscreen.
This object can be used to describe a series of segments to restrict
the region within touch events are reported or buttons with a specific
functionality.
This is of special interest if the touchscreen is shipped with a physical
overlay on top of it with a frame that hides some part of the original
touchscreen area. Printed buttons on that overlay are also a typical
use case.
A new touchscreen area is defined as a sub-node without a key code. If a
key code is defined in the sub-node, it will be interpreted as a button.
The x-origin and y-origin properties of a touchscreen area define the
offset of a new origin from where the touchscreen events are referenced.
This offset is applied to the events accordingly. The x-size and y-size
properties define the size of the touchscreen effective area.
The following example shows a new touchscreen area with the new origin
(0',0') for the touch events generated by the device.
Touchscreen (full area)
┌────────────────────────────────────────┐
│ ┌───────────────────────────────┐ │
│ │ │ │
│ ├ y-size │ │
│ │ │ │
│ │ touchscreen area │ │
│ │ (no key code) │ │
│ │ │ │
│ │ x-size │ │
│ ┌└──────────────┴────────────────┘ │
│(0',0') │
┌└────────────────────────────────────────┘
(0,0)
where (0',0') = (0+x-origin,0+y-origin)
Sub-nodes with key codes report the touch events on their surface as key
events instead.
The following example shows a touchscreen with a single button on it.
Touchscreen (full area)
┌───────────────────────────────────┐
│ │
│ │
│ ┌─────────┐ │
│ │button 0 │ │
│ │KEY_POWER│ │
│ └─────────┘ │
│ │
│ │
┌└───────────────────────────────────┘
(0,0)
Segments defining buttons and clipped toushcreen areas can be combined
as shown in the following example.
In that case only the events within the touchscreen area are reported
as touch events. Events within the button areas report their associated
key code. Any events outside the defined areas are ignored.
Touchscreen (full area)
┌─────────┬──────────────────────────────┐
│ │ │
│ │ ┌───────────────────────┐ │
│ button 0│ │ │ │
│KEY_POWER│ │ │ │
│ │ │ │ │
├─────────┤ │ touchscreen area │ │
│ │ │ (no key code) │ │
│ │ │ │ │
│ button 1│ │ │ │
│ KEY_INFO│ ┌└───────────────────────┘ │
│ │(0',0') │
┌└─────────┴──────────────────────────────┘
(0,0)
type: object
patternProperties:
'^segment-':
type: object
description:
Each segment is represented as a sub-node.
properties:
x-origin:
description: horizontal origin of the node area
$ref: /schemas/types.yaml#/definitions/uint32
y-origin:
description: vertical origin of the node area
$ref: /schemas/types.yaml#/definitions/uint32
x-size:
description: horizontal resolution of the node area
$ref: /schemas/types.yaml#/definitions/uint32
y-size:
description: vertical resolution of the node area
$ref: /schemas/types.yaml#/definitions/uint32
label:
description: descriptive name of the segment
$ref: /schemas/types.yaml#/definitions/string
linux,code: true
required:
- x-origin
- y-origin
- x-size
- y-size
unevaluatedProperties: false
dependencies:
touchscreen-size-x: [ touchscreen-size-y ]
touchscreen-size-y: [ touchscreen-size-x ]

39
Documentation/devicetree/bindings/input/touchscreen/tsc2007.txt
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@@ -1,39 +0,0 @@
* Texas Instruments tsc2007 touchscreen controller
Required properties:
- compatible: must be "ti,tsc2007".
- reg: I2C address of the chip.
- ti,x-plate-ohms: X-plate resistance in ohms.
Optional properties:
- gpios: the interrupt gpio the chip is connected to (through the penirq pin).
The penirq pin goes to low when the panel is touched.
(see GPIO binding[1] for more details).
- interrupts: (gpio) interrupt to which the chip is connected
(see interrupt binding[0]).
- ti,max-rt: maximum pressure.
- ti,fuzzx: specifies the absolute input fuzz x value.
If set, it will permit noise in the data up to +- the value given to the fuzz
parameter, that is used to filter noise from the event stream.
- ti,fuzzy: specifies the absolute input fuzz y value.
- ti,fuzzz: specifies the absolute input fuzz z value.
- ti,poll-period: how much time to wait (in milliseconds) before reading again the
values from the tsc2007.
[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[1]: Documentation/devicetree/bindings/gpio/gpio.txt
Example:
&i2c1 {
/* ... */
tsc2007@49 {
compatible = "ti,tsc2007";
reg = <0x49>;
interrupt-parent = <&gpio4>;
interrupts = <0x0 0x8>;
gpios = <&gpio4 0 0>;
ti,x-plate-ohms = <180>;
};
/* ... */
};

14
Documentation/devicetree/bindings/mailbox/allwinner,sun6i-a31-msgbox.yaml
View File

@@ -68,13 +68,13 @@ examples:
#include <dt-bindings/reset/sun8i-h3-ccu.h>
msgbox: mailbox@1c17000 {
compatible = "allwinner,sun8i-h3-msgbox",
"allwinner,sun6i-a31-msgbox";
reg = <0x01c17000 0x1000>;
clocks = <&ccu CLK_BUS_MSGBOX>;
resets = <&ccu RST_BUS_MSGBOX>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
compatible = "allwinner,sun8i-h3-msgbox",
"allwinner,sun6i-a31-msgbox";
reg = <0x01c17000 0x1000>;
clocks = <&ccu CLK_BUS_MSGBOX>;
resets = <&ccu RST_BUS_MSGBOX>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};
...

10
Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
View File

@@ -27,7 +27,7 @@ properties:
maxItems: 1
interrupts:
minItems: 3
maxItems: 3
description:
Contains the interrupt information corresponding to each of the 3 links
of MHU.
@@ -46,8 +46,8 @@ additionalProperties: false
examples:
- |
mailbox@c883c404 {
compatible = "amlogic,meson-gxbb-mhu";
reg = <0xc883c404 0x4c>;
interrupts = <208>, <209>, <210>;
#mbox-cells = <1>;
compatible = "amlogic,meson-gxbb-mhu";
reg = <0xc883c404 0x4c>;
interrupts = <208>, <209>, <210>;
#mbox-cells = <1>;
};

16
Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
View File

@@ -78,11 +78,11 @@ additionalProperties: false
examples:
- |
mailbox@77408000 {
compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
reg = <0x77408000 0x4000>;
interrupts = <1 583 4>, <1 584 4>, <1 585 4>, <1 586 4>;
interrupt-names = "send-empty", "send-not-empty",
"recv-empty", "recv-not-empty";
#mbox-cells = <0>;
};
mailbox@77408000 {
compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
reg = <0x77408000 0x4000>;
interrupts = <1 583 4>, <1 584 4>, <1 585 4>, <1 586 4>;
interrupt-names = "send-empty", "send-not-empty",
"recv-empty", "recv-not-empty";
#mbox-cells = <0>;
};

68
Documentation/devicetree/bindings/mailbox/aspeed,ast2700-mailbox.yaml Normal file
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@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/aspeed,ast2700-mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASPEED AST2700 mailbox controller
maintainers:
- Jammy Huang <jammy_huang@aspeedtech.com>
description: >
ASPEED AST2700 has multiple processors that need to communicate with each
other. The mailbox controller provides a way for these processors to send
messages to each other. It is a hardware-based inter-processor communication
mechanism that allows processors to send and receive messages through
dedicated channels.
The mailbox's tx/rx are independent, meaning that one processor can send a
message while another processor is receiving a message simultaneously.
There are 4 channels available for both tx and rx operations. Each channel
has a FIFO buffer that can hold messages of a fixed size (32 bytes in this
case).
The mailbox controller also supports interrupt generation, allowing
processors to notify each other when a message is available or when an event
occurs.
properties:
compatible:
const: aspeed,ast2700-mailbox
reg:
items:
- description: TX control register
- description: RX control register
reg-names:
items:
- const: tx
- const: rx
interrupts:
maxItems: 1
"#mbox-cells":
const: 1
required:
- compatible
- reg
- reg-names
- interrupts
- "#mbox-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox@12c1c200 {
compatible = "aspeed,ast2700-mailbox";
reg = <0x12c1c200 0x100>, <0x12c1c300 0x100>;
reg-names = "tx", "rx";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};

64
Documentation/devicetree/bindings/mailbox/brcm,bcm74110-mbox.yaml Normal file
View File

@@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/brcm,bcm74110-mbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM74110 Mailbox
maintainers:
- Justin Chen <justin.chen@broadcom.com>
- Florian Fainelli <florian.fainelli@broadcom.com>
description: Broadcom mailbox hardware first introduced with 74110
properties:
compatible:
enum:
- brcm,bcm74110-mbox
reg:
maxItems: 1
interrupts:
items:
- description: RX doorbell and watermark interrupts
- description: TX doorbell and watermark interrupts
"#mbox-cells":
const: 2
description:
The first cell is channel type and second cell is shared memory slot
brcm,rx:
$ref: /schemas/types.yaml#/definitions/uint32
description: RX Mailbox number
brcm,tx:
$ref: /schemas/types.yaml#/definitions/uint32
description: TX Mailbox number
required:
- compatible
- reg
- interrupts
- "#mbox-cells"
- brcm,rx
- brcm,tx
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox@a552000 {
compatible = "brcm,bcm74110-mbox";
reg = <0xa552000 0x1104>;
interrupts = <GIC_SPI 0x67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 0x66 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <0x2>;
brcm,rx = <0x7>;
brcm,tx = <0x6>;
};

9
Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
View File

@@ -59,9 +59,6 @@ description: |
<dt-bindings/mailbox/tegra186-hsp.h>
properties:
$nodename:
pattern: "^hsp@[0-9a-f]+$"
compatible:
oneOf:
- enum:
@@ -131,14 +128,10 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
hsp_top0: hsp@3c00000 {
mailbox@3c00000 {
compatible = "nvidia,tegra186-hsp";
reg = <0x03c00000 0xa0000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "doorbell";
#mbox-cells = <2>;
};
client {
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
};

9
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
View File

@@ -251,7 +251,7 @@ examples:
# Example apcs with msm8996
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
apcs_glb: mailbox@9820000 {
mailbox@9820000 {
compatible = "qcom,msm8996-apcs-hmss-global";
reg = <0x9820000 0x1000>;
@@ -259,13 +259,6 @@ examples:
#clock-cells = <0>;
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
};
# Example apcs with qcs404
- |
#define GCC_APSS_AHB_CLK_SRC 1

1
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
View File

@@ -24,6 +24,7 @@ properties:
compatible:
items:
- enum:
- qcom,milos-ipcc
- qcom,qcs8300-ipcc
- qcom,qdu1000-ipcc
- qcom,sa8255p-ipcc

10
Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml
View File

@@ -242,7 +242,7 @@ examples:
- |
/* OMAP4 */
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox: mailbox@4a0f4000 {
mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -260,13 +260,9 @@ examples:
};
};
dsp {
mboxes = <&mailbox &mbox_dsp>;
};
- |
/* AM33xx */
mailbox1: mailbox@480c8000 {
mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480c8000 0x200>;
interrupts = <77>;
@@ -283,7 +279,7 @@ examples:
- |
/* AM65x */
mailbox0_cluster0: mailbox@31f80000 {
mailbox@31f80000 {
compatible = "ti,am654-mailbox";
reg = <0x31f80000 0x200>;
#mbox-cells = <1>;

18
Documentation/devicetree/bindings/mailbox/ti,secure-proxy.yaml
View File

@@ -36,7 +36,7 @@ properties:
- const: scfg
reg:
minItems: 3
maxItems: 3
interrupt-names:
minItems: 1
@@ -68,12 +68,12 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
secure_proxy: mailbox@32c00000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x32c00000 0x100000>,
<0x32400000 0x100000>,
<0x32800000 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x32c00000 0x100000>,
<0x32400000 0x100000>,
<0x32800000 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};

2
Documentation/devicetree/bindings/net/adi,adin.yaml
View File

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices ADIN1200/ADIN1300 PHY
maintainers:
- Alexandru Tachici <alexandru.tachici@analog.com>
- Marcelo Schmitt <marcelo.schmitt@analog.com>
description: |
Bindings for Analog Devices Industrial Ethernet PHYs

2
Documentation/devicetree/bindings/net/adi,adin1110.yaml
View File

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADI ADIN1110 MAC-PHY
maintainers:
- Alexandru Tachici <alexandru.tachici@analog.com>
- Marcelo Schmitt <marcelo.schmitt@analog.com>
description: |
The ADIN1110 is a low power single port 10BASE-T1L MAC-

9
Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml
View File

@@ -15,11 +15,18 @@ allOf:
properties:
compatible:
oneOf:
- const: amlogic,pinctrl-a4
- enum:
- amlogic,pinctrl-a4
- amlogic,pinctrl-s6
- amlogic,pinctrl-s7
- items:
- enum:
- amlogic,pinctrl-a5
- const: amlogic,pinctrl-a4
- items:
- enum:
- amlogic,pinctrl-s7d
- const: amlogic,pinctrl-s7
"#address-cells":
const: 2

156
Documentation/devicetree/bindings/pinctrl/eswin,eic7700-pinctrl.yaml Normal file
View File

@@ -0,0 +1,156 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/eswin,eic7700-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Eswin Eic7700 Pinctrl
maintainers:
- Yulin Lu <luyulin@eswincomputing.com>
allOf:
- $ref: pinctrl.yaml#
description: |
eic7700 pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for one or
more pins. This configuration can include the mux function to select on those pin(s),
and various pin configuration parameters, such as input-enable, pull-up, etc.
properties:
compatible:
const: eswin,eic7700-pinctrl
reg:
maxItems: 1
vrgmii-supply:
description:
Regulator supply for the RGMII interface IO power domain.
This property should reference a regulator that provides either 1.8V or 3.3V,
depending on the board-level voltage configuration required by the RGMII interface.
patternProperties:
'-grp$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
properties:
pins:
description:
For eic7700, specifies the name(s) of one or more pins to be configured by
this node.
items:
enum: [ chip_mode, mode_set0, mode_set1, mode_set2, mode_set3, xin,
rst_out_n, key_reset_n, gpio0, por_sel, jtag0_tck, jtag0_tms,
jtag0_tdi, jtag0_tdo, gpio5, spi2_cs0_n, jtag1_tck, jtag1_tms,
jtag1_tdi, jtag1_tdo, gpio11, spi2_cs1_n, pcie_clkreq_n,
pcie_wake_n, pcie_perst_n, hdmi_scl, hdmi_sda, hdmi_cec,
jtag2_trst, rgmii0_clk_125, rgmii0_txen, rgmii0_txclk,
rgmii0_txd0, rgmii0_txd1, rgmii0_txd2, rgmii0_txd3, i2s0_bclk,
i2s0_wclk, i2s0_sdi, i2s0_sdo, i2s_mclk, rgmii0_rxclk,
rgmii0_rxdv, rgmii0_rxd0, rgmii0_rxd1, rgmii0_rxd2, rgmii0_rxd3,
i2s2_bclk, i2s2_wclk, i2s2_sdi, i2s2_sdo, gpio27, gpio28, gpio29,
rgmii0_mdc, rgmii0_mdio, rgmii0_intb, rgmii1_clk_125, rgmii1_txen,
rgmii1_txclk, rgmii1_txd0, rgmii1_txd1, rgmii1_txd2, rgmii1_txd3,
i2s1_bclk, i2s1_wclk, i2s1_sdi, i2s1_sdo, gpio34, rgmii1_rxclk,
rgmii1_rxdv, rgmii1_rxd0, rgmii1_rxd1, rgmii1_rxd2, rgmii1_rxd3,
spi1_cs0_n, spi1_clk, spi1_d0, spi1_d1, spi1_d2, spi1_d3, spi1_cs1_n,
rgmii1_mdc, rgmii1_mdio, rgmii1_intb, usb0_pwren, usb1_pwren,
i2c0_scl, i2c0_sda, i2c1_scl, i2c1_sda, i2c2_scl, i2c2_sda,
i2c3_scl, i2c3_sda, i2c4_scl, i2c4_sda, i2c5_scl, i2c5_sda,
uart0_tx, uart0_rx, uart1_tx, uart1_rx, uart1_cts, uart1_rts,
uart2_tx, uart2_rx, jtag2_tck, jtag2_tms, jtag2_tdi, jtag2_tdo,
fan_pwm, fan_tach, mipi_csi0_xvs, mipi_csi0_xhs, mipi_csi0_mclk,
mipi_csi1_xvs, mipi_csi1_xhs, mipi_csi1_mclk, mipi_csi2_xvs,
mipi_csi2_xhs, mipi_csi2_mclk, mipi_csi3_xvs, mipi_csi3_xhs,
mipi_csi3_mclk, mipi_csi4_xvs, mipi_csi4_xhs, mipi_csi4_mclk,
mipi_csi5_xvs, mipi_csi5_xhs, mipi_csi5_mclk, spi3_cs_n, spi3_clk,
spi3_di, spi3_do, gpio92, gpio93, s_mode, gpio95, spi0_cs_n,
spi0_clk, spi0_d0, spi0_d1, spi0_d2, spi0_d3, i2c10_scl,
i2c10_sda, i2c11_scl, i2c11_sda, gpio106, boot_sel0, boot_sel1,
boot_sel2, boot_sel3, gpio111, lpddr_ref_clk ]
function:
description:
Specify the alternative function to be configured for the
given pins.
enum: [ disabled, boot_sel, chip_mode, emmc, fan_tach,
gpio, hdmi, i2c, i2s, jtag, ddr_ref_clk_sel,
lpddr_ref_clk, mipi_csi, osc, pcie, pwm,
rgmii, reset, sata, sdio, spi, s_mode, uart, usb ]
input-schmitt-enable: true
input-schmitt-disable: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
input-enable: true
input-disable: true
drive-strength-microamp: true
required:
- pins
additionalProperties: false
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
- if:
properties:
pins:
anyOf:
- pattern: '^rgmii'
- const: lpddr_ref_clk
then:
properties:
drive-strength-microamp:
enum: [3000, 6000, 9000, 12000, 15000, 18000, 21000, 24000]
else:
properties:
drive-strength-microamp:
enum: [6000, 9000, 12000, 15000, 18000, 21000, 24000, 27000]
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
pinctrl@51600080 {
compatible = "eswin,eic7700-pinctrl";
reg = <0x51600080 0x1fff80>;
vrgmii-supply = <&vcc_1v8>;
dev-active-grp {
/* group node defining 1 standard pin */
gpio10-pins {
pins = "jtag1_tdo";
function = "gpio";
input-enable;
bias-pull-up;
};
/* group node defining 2 I2C pins */
i2c6-pins {
pins = "uart1_cts", "uart1_rts";
function = "i2c";
};
};
};

213
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@@ -0,0 +1,213 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8189-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT8189 Pin Controller
maintainers:
- Lei Xue <lei.xue@mediatek.com>
- Cathy Xu <ot_cathy.xu@mediatek.com>
description:
The MediaTek's MT8189 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8189-pinctrl
reg:
items:
- description: gpio base
- description: lm group IO
- description: rb0 group IO
- description: rb1 group IO
- description: bm0 group IO
- description: bm1 group IO
- description: bm2 group IO
- description: lt0 group IO
- description: lt1 group IO
- description: rt group IO
- description: eint0 group IO
- description: eint1 group IO
- description: eint2 group IO
- description: eint3 group IO
- description: eint4 group IO
reg-names:
items:
- const: base
- const: lm
- const: rb0
- const: rb1
- const: bm0
- const: bm1
- const: bm2
- const: lt0
- const: lt1
- const: rt
- const: eint0
- const: eint1
- const: eint2
- const: eint3
- const: eint4
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
maxItems: 1
gpio-line-names: true
# PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'^pins':
type: object
$ref: /schemas/pinctrl/pincfg-node.yaml
additionalProperties: false
description:
A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
properties:
pinmux:
description:
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h
directly, for this SoC.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
bias-pull-down:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt8189 pull down PUPD/R0/R1 type define value.
- enum: [75000, 5000]
description: mt8189 pull down RSEL type si unit value(ohm).
description: |
For pull down type is normal, it doesn't need add R1R0 define
and resistance value.
For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
"MTK_PUPD_SET_R1R0_11" define in mt8189.
For pull down type is PD/RSEL, it can add resistance value(ohm)
to set different resistance by identifying property
"mediatek,rsel-resistance-in-si-unit".
bias-pull-up:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt8189 pull up PUPD/R0/R1 type define value.
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000]
description: mt8189 pull up RSEL type si unit value(ohm).
description: |
For pull up type is normal, it don't need add R1R0 define
and resistance value.
For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
"MTK_PUPD_SET_R1R0_11" define in mt8189.
For pull up type is PU/RSEL, it can add resistance value(ohm)
to set different resistance by identifying property
"mediatek,rsel-resistance-in-si-unit".
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 2)
#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 2)
pio: pinctrl@10005000 {
compatible = "mediatek,mt8189-pinctrl";
reg = <0x10005000 0x1000>,
<0x11b50000 0x1000>,
<0x11c50000 0x1000>,
<0x11c60000 0x1000>,
<0x11d20000 0x1000>,
<0x11d30000 0x1000>,
<0x11d40000 0x1000>,
<0x11e20000 0x1000>,
<0x11e30000 0x1000>,
<0x11f20000 0x1000>,
<0x11ce0000 0x1000>,
<0x11de0000 0x1000>,
<0x11e60000 0x1000>,
<0x1c01e000 0x1000>,
<0x11f00000 0x1000>;
reg-names = "base", "lm", "rb0", "rb1", "bm0" , "bm1",
"bm2", "lt0", "lt1", "rt", "eint0", "eint1",
"eint2", "eint3", "eint4";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 182>;
interrupt-controller;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
i2c0-pins {
pins {
pinmux = <PINMUX_GPIO51__FUNC_SCL0>,
<PINMUX_GPIO52__FUNC_SDA0>;
bias-disable;
};
};
};

71
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@@ -1,71 +0,0 @@
NXP LPC18xx/43xx SCU pin controller Device Tree Bindings
--------------------------------------------------------
Required properties:
- compatible : Should be "nxp,lpc1850-scu"
- reg : Address and length of the register set for the device
- clocks : Clock specifier (see clock bindings for details)
The lpc1850-scu driver uses the generic pin multiplexing and generic pin
configuration documented in pinctrl-bindings.txt.
The following generic nodes are supported:
- function
- pins
- bias-disable
- bias-pull-up
- bias-pull-down
- drive-strength
- input-enable
- input-disable
- input-schmitt-enable
- input-schmitt-disable
- slew-rate
NXP specific properties:
- nxp,gpio-pin-interrupt : Assign pin to gpio pin interrupt controller
irq number 0 to 7. See example below.
Not all pins support all properties so either refer to the NXP 1850/4350
user manual or the pin table in the pinctrl-lpc18xx driver for supported
pin properties.
Example:
pinctrl: pinctrl@40086000 {
compatible = "nxp,lpc1850-scu";
reg = <0x40086000 0x1000>;
clocks = <&ccu1 CLK_CPU_SCU>;
i2c0_pins: i2c0-pins {
i2c0_pins_cfg {
pins = "i2c0_scl", "i2c0_sda";
function = "i2c0";
input-enable;
};
};
uart0_pins: uart0-pins {
uart0_rx_cfg {
pins = "pf_11";
function = "uart0";
bias-disable;
input-enable;
};
uart0_tx_cfg {
pins = "pf_10";
function = "uart0";
bias-disable;
};
};
gpio_joystick_pins: gpio-joystick-pins {
gpio_joystick_1_cfg {
pins = "p9_0";
function = "gpio";
nxp,gpio-pin-interrupt = <0>;
input-enable;
bias-disable;
};
};
};

79
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@@ -0,0 +1,79 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nxp,lpc1850-scu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC18xx/43xx SCU pin controller
description:
Not all pins support all pin generic node properties so either refer to
the NXP 1850/4350 user manual or the pin table in the pinctrl-lpc18xx
driver for supported pin properties.
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: nxp,lpc1850-scu
reg:
maxItems: 1
clocks:
maxItems: 1
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'_cfg$':
type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
unevaluatedProperties: false
properties:
nxp,gpio-pin-interrupt:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
description:
Assign pin to gpio pin interrupt controller
irq number 0 to 7. See example below.
required:
- compatible
- reg
- clocks
allOf:
- $ref: pinctrl.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/lpc18xx-ccu.h>
pinctrl@40086000 {
compatible = "nxp,lpc1850-scu";
reg = <0x40086000 0x1000>;
clocks = <&ccu1 CLK_CPU_SCU>;
gpio-joystick-pins {
gpio-joystick-1_cfg {
pins = "p9_0";
function = "gpio";
nxp,gpio-pin-interrupt = <0>;
input-enable;
bias-disable;
};
};
};

133
Documentation/devicetree/bindings/pinctrl/qcom,milos-tlmm.yaml Normal file
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@@ -0,0 +1,133 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,milos-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Milos TLMM block
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Milos SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,milos-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 84
gpio-line-names:
maxItems: 167
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-milos-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-milos-tlmm-state"
additionalProperties: false
$defs:
qcom-milos-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-7])$"
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
audio_ext_mclk1, audio_ref_clk, cam_mclk, cci_async_in0,
cci_i2c_scl, cci_i2c_sda, cci_timer, coex_uart1_rx,
coex_uart1_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail,
ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot,
egpio, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, i2s0_data0,
i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync,
mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk_req_n,
pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
qdss_gpio, qlink0_enable, qlink0_request, qlink0_wmss,
qlink1_enable, qlink1_request, qlink1_wmss, qspi0, qup0_se0,
qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, qup0_se6,
qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5,
qup1_se6, resout_gpio_n, sd_write_protect, sdc1_clk, sdc1_cmd,
sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data,
sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tgu_ch0_trigout,
tgu_ch1_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
uim0_present, uim0_reset, uim1_clk_mira, uim1_clk_mirb,
uim1_data_mira, uim1_data_mirb, uim1_present_mira,
uim1_present_mirb, uim1_reset_mira, uim1_reset_mirb, usb0_hs,
usb0_phy_ps, vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw,
wcn_sw_ctrl ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f100000 {
compatible = "qcom,milos-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 168>;
gpio-wo-state {
pins = "gpio1";
function = "gpio";
};
qup-uart5-default-state {
pins = "gpio25", "gpio26";
function = "qup0_se5";
drive-strength = <2>;
bias-disable;
};
};
...

4
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@@ -27,6 +27,7 @@ properties:
- qcom,pm6450-gpio
- qcom,pm7250b-gpio
- qcom,pm7325-gpio
- qcom,pm7550-gpio
- qcom,pm7550ba-gpio
- qcom,pm8005-gpio
- qcom,pm8018-gpio
@@ -64,6 +65,7 @@ properties:
- qcom,pmi8994-gpio
- qcom,pmi8998-gpio
- qcom,pmih0108-gpio
- qcom,pmiv0104-gpio
- qcom,pmk8350-gpio
- qcom,pmk8550-gpio
- qcom,pmm8155au-gpio
@@ -228,6 +230,7 @@ allOf:
- qcom,pmc8180-gpio
- qcom,pmc8380-gpio
- qcom,pmi8994-gpio
- qcom,pmiv0104-gpio
- qcom,pmm8155au-gpio
then:
properties:
@@ -261,6 +264,7 @@ allOf:
- qcom,pm660l-gpio
- qcom,pm6150l-gpio
- qcom,pm7250b-gpio
- qcom,pm7550-gpio
- qcom,pm8038-gpio
- qcom,pm8150b-gpio
- qcom,pm8150l-gpio

2
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
View File

@@ -135,7 +135,7 @@ additionalProperties:
description:
Pin bank index.
- minimum: 0
maximum: 13
maximum: 14
description:
Mux 0 means GPIO and mux 1 to N means
the specific device function.

187
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@@ -0,0 +1,187 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) STMicroelectronics 2025.
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/st,stm32-hdp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STM32 Hardware Debug Port Mux/Config
maintainers:
- Clément LE GOFFIC <legoffic.clement@gmail.com>
description:
STMicroelectronics's STM32 MPUs integrate a Hardware Debug Port (HDP).
It allows to output internal signals on SoC's GPIO.
properties:
compatible:
enum:
- st,stm32mp131-hdp
- st,stm32mp151-hdp
- st,stm32mp251-hdp
reg:
maxItems: 1
clocks:
maxItems: 1
patternProperties:
"^hdp[0-7]-pins$":
type: object
$ref: pinmux-node.yaml#
additionalProperties: false
properties:
pins:
pattern: '^HDP[0-7]$'
function: true
required:
- function
- pins
allOf:
- $ref: pinctrl.yaml#
- if:
properties:
compatible:
contains:
const: st,stm32mp131-hdp
then:
patternProperties:
"^hdp[0-7]-pins$":
properties:
function:
enum: [ pwr_pwrwake_sys, pwr_stop_forbidden, pwr_stdby_wakeup, pwr_encomp_vddcore,
bsec_out_sec_niden, aiec_sys_wakeup, none, ddrctrl_lp_req,
pwr_ddr_ret_enable_n, dts_clk_ptat, sram3ctrl_tamp_erase_act, gpoval0,
pwr_sel_vth_vddcpu, pwr_mpu_ram_lowspeed, ca7_naxierrirq, pwr_okin_mr,
bsec_out_sec_dbgen, aiec_c1_wakeup, rcc_pwrds_mpu, ddrctrl_dfi_ctrlupd_req,
ddrctrl_cactive_ddrc_asr, sram3ctrl_hw_erase_act, nic400_s0_bready, gpoval1,
pwr_pwrwake_mpu, pwr_mpu_clock_disable_ack, ca7_ndbgreset_i,
bsec_in_rstcore_n, bsec_out_sec_bsc_dis, ddrctrl_dfi_init_complete,
ddrctrl_perf_op_is_refresh, ddrctrl_gskp_dfi_lp_req, sram3ctrl_sw_erase_act,
nic400_s0_bvalid, gpoval2, pwr_sel_vth_vddcore, pwr_mpu_clock_disable_req,
ca7_npmuirq0, ca7_nfiqout0, bsec_out_sec_dftlock, bsec_out_sec_jtag_dis,
rcc_pwrds_sys, sram3ctrl_tamp_erase_req, ddrctrl_stat_ddrc_reg_selfref_type0,
dts_valobus1_0, dts_valobus2_0, tamp_potential_tamp_erfcfg, nic400_s0_wready,
nic400_s0_rready, gpoval3, pwr_stop2_active, ca7_nl2reset_i,
ca7_npreset_varm_i, bsec_out_sec_dften, bsec_out_sec_dbgswenable,
eth1_out_pmt_intr_o, eth2_out_pmt_intr_o, ddrctrl_stat_ddrc_reg_selfref_type1,
ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, tamp_nreset_sram_ercfg,
nic400_s0_wlast, nic400_s0_rlast, gpoval4, ca7_standbywfil2,
pwr_vth_vddcore_ack, ca7_ncorereset_i, ca7_nirqout0, bsec_in_pwrok,
bsec_out_sec_deviceen, eth1_out_lpi_intr_o, eth2_out_lpi_intr_o,
ddrctrl_cactive_ddrc, ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2,
pka_pka_itamp_out, nic400_s0_wvalid, nic400_s0_rvalid, gpoval5,
ca7_standbywfe0, pwr_vth_vddcpu_ack, ca7_evento, bsec_in_tamper_det,
bsec_out_sec_spniden, eth1_out_mac_speed_o1, eth2_out_mac_speed_o1,
ddrctrl_csysack_ddrc, ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3,
saes_tamper_out, nic400_s0_awready, nic400_s0_arready, gpoval6,
ca7_standbywfi0, pwr_rcc_vcpu_rdy, ca7_eventi, ca7_dbgack0, bsec_out_fuse_ok,
bsec_out_sec_spiden, eth1_out_mac_speed_o0, eth2_out_mac_speed_o0,
ddrctrl_csysreq_ddrc, ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4,
rng_tamper_out, nic400_s0_awavalid, nic400_s0_aravalid, gpoval7 ]
- if:
properties:
compatible:
contains:
const: st,stm32mp151-hdp
then:
patternProperties:
"^hdp[0-7]-pins$":
properties:
function:
enum: [ pwr_pwrwake_sys, cm4_sleepdeep, pwr_stdby_wkup, pwr_encomp_vddcore,
bsec_out_sec_niden, none, rcc_cm4_sleepdeep, gpu_dbg7, ddrctrl_lp_req,
pwr_ddr_ret_enable_n, dts_clk_ptat, gpoval0, pwr_pwrwake_mcu, cm4_halted,
ca7_naxierrirq, pwr_okin_mr, bsec_out_sec_dbgen, exti_sys_wakeup,
rcc_pwrds_mpu, gpu_dbg6, ddrctrl_dfi_ctrlupd_req, ddrctrl_cactive_ddrc_asr,
gpoval1, pwr_pwrwake_mpu, cm4_rxev, ca7_npmuirq1, ca7_nfiqout1,
bsec_in_rstcore_n, exti_c2_wakeup, rcc_pwrds_mcu, gpu_dbg5,
ddrctrl_dfi_init_complete, ddrctrl_perf_op_is_refresh,
ddrctrl_gskp_dfi_lp_req, gpoval2, pwr_sel_vth_vddcore, cm4_txev, ca7_npmuirq0,
ca7_nfiqout0, bsec_out_sec_dftlock, exti_c1_wakeup, rcc_pwrds_sys, gpu_dbg4,
ddrctrl_stat_ddrc_reg_selfref_type0, ddrctrl_cactive_1, dts_valobus1_0,
dts_valobus2_0, gpoval3, pwr_mpu_pdds_not_cstbydis, cm4_sleeping, ca7_nreset1,
ca7_nirqout1, bsec_out_sec_dften, bsec_out_sec_dbgswenable,
eth_out_pmt_intr_o, gpu_dbg3, ddrctrl_stat_ddrc_reg_selfref_type1,
ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, gpoval4, ca7_standbywfil2,
pwr_vth_vddcore_ack, ca7_nreset0, ca7_nirqout0, bsec_in_pwrok,
bsec_out_sec_deviceen, eth_out_lpi_intr_o, gpu_dbg2, ddrctrl_cactive_ddrc,
ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2, gpoval5,
ca7_standbywfi1, ca7_standbywfe1, ca7_evento, ca7_dbgack1,
bsec_out_sec_spniden, eth_out_mac_speed_o1, gpu_dbg1, ddrctrl_csysack_ddrc,
ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3, gpoval6,
ca7_standbywfi0, ca7_standbywfe0, ca7_dbgack0, bsec_out_fuse_ok,
bsec_out_sec_spiden, eth_out_mac_speed_o0, gpu_dbg0, ddrctrl_csysreq_ddrc,
ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4, gpoval7 ]
- if:
properties:
compatible:
contains:
const: st,stm32mp251-hdp
then:
patternProperties:
"^hdp[0-7]-pins$":
properties:
function:
enum: [ pwr_pwrwake_sys, cpu2_sleep_deep, bsec_out_tst_sdr_unlock_or_disable_scan,
bsec_out_nidenm, bsec_out_nidena, cpu2_state_0, rcc_pwrds_sys, gpu_dbg7,
ddrss_csysreq_ddrc, ddrss_dfi_phyupd_req, cpu3_sleep_deep,
d2_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_0,
pcie_usb_cxpl_debug_info_ei_8, d3_state_0, gpoval0, pwr_pwrwake_cpu2,
cpu2_halted, cpu2_state_1, bsec_out_dbgenm, bsec_out_dbgena, exti1_sys_wakeup,
rcc_pwrds_cpu2, gpu_dbg6, ddrss_csysack_ddrc, ddrss_dfi_phymstr_req,
cpu3_halted, d2_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_1,
pcie_usb_cxpl_debug_info_ei_9, d3_state_1, gpoval1, pwr_pwrwake_cpu1,
cpu2_rxev, cpu1_npumirq1, cpu1_nfiqout1, bsec_out_shdbgen, exti1_cpu2_wakeup,
rcc_pwrds_cpu1, gpu_dbg5, ddrss_cactive_ddrc, ddrss_dfi_lp_req, cpu3_rxev,
hpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_2,
pcie_usb_cxpl_debug_info_ei_10, d3_state_2, gpoval2, pwr_sel_vth_vddcpu,
cpu2_txev, cpu1_npumirq0, cpu1_nfiqout0, bsec_out_ddbgen, exti1_cpu1_wakeup,
cpu3_state_0, gpu_dbg4, ddrss_mcdcg_en, ddrss_dfi_freq_0, cpu3_txev,
hpdma2_clk_bus_req, pcie_usb_cxpl_debug_info_ei_3,
pcie_usb_cxpl_debug_info_ei_11, d1_state_0, gpoval3, pwr_sel_vth_vddcore,
cpu2_sleeping, cpu1_evento, cpu1_nirqout1, bsec_out_spnidena, exti2_d3_wakeup,
eth1_out_pmt_intr_o, gpu_dbg3, ddrss_dphycg_en, ddrss_obsp0, cpu3_sleeping,
hpdma3_clk_bus_req, pcie_usb_cxpl_debug_info_ei_4,
pcie_usb_cxpl_debug_info_ei_12, d1_state_1, gpoval4, cpu1_standby_wfil2,
none, cpu1_nirqout0, bsec_out_spidena, exti2_cpu3_wakeup, eth1_out_lpi_intr_o,
gpu_dbg2, ddrctrl_dfi_init_start, ddrss_obsp1, cpu3_state_1,
d3_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_5,
pcie_usb_cxpl_debug_info_ei_13, d1_state_2, gpoval5, cpu1_standby_wfi1,
cpu1_standby_wfe1, cpu1_halted1, cpu1_naxierrirq, bsec_out_spnidenm,
exti2_cpu2_wakeup, eth2_out_pmt_intr_o, gpu_dbg1, ddrss_dfi_init_complete,
ddrss_obsp2, d2_state_0, d3_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_6,
pcie_usb_cxpl_debug_info_ei_14, cpu1_state_0, gpoval6, cpu1_standby_wfi0,
cpu1_standby_wfe0, cpu1_halted0, bsec_out_spidenm, exti2_cpu1__wakeup,
eth2_out_lpi_intr_o, gpu_dbg0, ddrss_dfi_ctrlupd_req, ddrss_obsp3, d2_state_1,
lpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_7,
pcie_usb_cxpl_debug_info_ei_15, cpu1_state_1, gpoval7 ]
required:
- compatible
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
pinctrl@54090000 {
compatible = "st,stm32mp151-hdp";
reg = <0x54090000 0x400>;
clocks = <&rcc HDP>;
pinctrl-names = "default";
pinctrl-0 = <&hdp2_gpo>;
hdp2_gpo: hdp2-pins {
function = "gpoval2";
pins = "HDP2";
};
};

25
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
View File

@@ -32,13 +32,16 @@ properties:
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges: true
pins-are-numbered:
$ref: /schemas/types.yaml#/definitions/flag
deprecated: true
hwlocks: true
interrupts:
@@ -67,22 +70,29 @@ patternProperties:
additionalProperties: false
properties:
gpio-controller: true
'#gpio-cells':
const: 2
interrupt-controller: true
'#interrupt-cells':
const: 2
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
gpio-line-names: true
gpio-ranges:
minItems: 1
maxItems: 16
ngpios:
description:
Number of available gpios in a bank.
@@ -160,9 +170,13 @@ patternProperties:
* ...
* 16 : Alternate Function 15
* 17 : Analog
* 18 : Reserved
To simplify the usage, macro is available to generate "pinmux" field.
This macro is available here:
- include/dt-bindings/pinctrl/stm32-pinfunc.h
Setting the pinmux's function to the Reserved (RSVD) value is used to inform
the driver that it shall not apply the mux setting. This can be used to
reserve some pins, for example to a co-processor not running Linux.
Some examples of using macro:
/* GPIO A9 set as alternate function 2 */
... {
@@ -176,21 +190,32 @@ patternProperties:
... {
pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
};
/* GPIO A9 reserved for co-processor */
... {
pinmux = <STM32_PINMUX('A', 9, RSVD)>;
};
bias-disable:
type: boolean
bias-pull-down:
type: boolean
bias-pull-up:
type: boolean
drive-push-pull:
type: boolean
drive-open-drain:
type: boolean
output-low:
type: boolean
output-high:
type: boolean
slew-rate:
description: |
0: Low speed

11
Documentation/devicetree/bindings/rtc/amlogic,a4-rtc.yaml
View File

@@ -16,9 +16,14 @@ allOf:
properties:
compatible:
enum:
- amlogic,a4-rtc
- amlogic,a5-rtc
oneOf:
- enum:
- amlogic,a4-rtc
- amlogic,a5-rtc
- items:
- enum:
- amlogic,c3-rtc
- const: amlogic,a5-rtc
reg:
maxItems: 1

7
Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml
View File

@@ -18,7 +18,12 @@ allOf:
properties:
compatible:
const: nxp,lpc1788-rtc
oneOf:
- items:
- enum:
- nxp,lpc1850-rtc
- const: nxp,lpc1788-rtc
- const: nxp,lpc1788-rtc
reg:
maxItems: 1

49
Documentation/devicetree/bindings/rtc/nxp,lpc3220-rtc.yaml Normal file
View File

@@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/nxp,lpc3220-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC32xx SoC Real-time Clock
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
enum:
- nxp,lpc3220-rtc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
start-year: true
required:
- compatible
- reg
allOf:
- $ref: rtc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/lpc32xx-clock.h>
rtc@40024000 {
compatible = "nxp,lpc3220-rtc";
reg = <0x40024000 0x1000>;
interrupt-parent = <&sic1>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_RTC>;
};

33
Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml
View File

@@ -12,6 +12,7 @@ maintainers:
properties:
compatible:
enum:
- microcrystal,rv8063
- microcrystal,rv8263
- nxp,pcf85063
- nxp,pcf85063a
@@ -44,13 +45,19 @@ properties:
wakeup-source: true
spi-cs-high: true
spi-3wire: true
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
- $ref: rtc.yaml#
- if:
properties:
compatible:
contains:
enum:
- microcrystal,rv8063
- microcrystal,rv8263
then:
properties:
@@ -65,12 +72,23 @@ allOf:
properties:
quartz-load-femtofarads:
const: 7000
- if:
properties:
compatible:
not:
contains:
enum:
- microcrystal,rv8063
then:
properties:
spi-cs-high: false
spi-3wire: false
required:
- compatible
- reg
additionalProperties: false
unevaluatedProperties: false
examples:
- |
@@ -90,3 +108,16 @@ examples:
};
};
};
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
rtc@0 {
compatible = "microcrystal,rv8063";
reg = <0>;
spi-cs-high;
spi-3wire;
};
};

2
Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-rtc.yaml → Documentation/devicetree/bindings/rtc/sophgo,cv1800b-rtc.yaml
View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sophgo/sophgo,cv1800b-rtc.yaml#
$id: http://devicetree.org/schemas/rtc/sophgo,cv1800b-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Real Time Clock of the Sophgo CV1800 SoC

2
Documentation/devicetree/bindings/rtc/trivial-rtc.yaml
View File

@@ -63,8 +63,6 @@ properties:
- microcrystal,rv3029
# Real Time Clock
- microcrystal,rv8523
# NXP LPC32xx SoC Real-time Clock
- nxp,lpc3220-rtc
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
- ricoh,r2025sd
# I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC

46
Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
View File

@@ -9,21 +9,20 @@ title: Mediatek Universal Flash Storage (UFS) Controller
maintainers:
- Stanley Chu <stanley.chu@mediatek.com>
allOf:
- $ref: ufs-common.yaml
properties:
compatible:
enum:
- mediatek,mt8183-ufshci
- mediatek,mt8192-ufshci
- mediatek,mt8195-ufshci
clocks:
maxItems: 1
minItems: 1
maxItems: 8
clock-names:
items:
- const: ufs
minItems: 1
maxItems: 8
phys:
maxItems: 1
@@ -33,6 +32,10 @@ properties:
vcc-supply: true
mediatek,ufs-disable-mcq:
$ref: /schemas/types.yaml#/definitions/flag
description: The mask to disable MCQ (Multi-Circular Queue) for UFS host.
required:
- compatible
- clocks
@@ -43,6 +46,37 @@ required:
unevaluatedProperties: false
allOf:
- $ref: ufs-common.yaml
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt8195-ufshci
then:
properties:
clocks:
minItems: 8
clock-names:
items:
- const: ufs
- const: ufs_aes
- const: ufs_tick
- const: unipro_sysclk
- const: unipro_tick
- const: unipro_mp_bclk
- const: ufs_tx_symbol
- const: ufs_mem_sub
else:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: ufs
examples:
- |
#include <dt-bindings/clock/mt8183-clk.h>

6
Documentation/filesystems/f2fs.rst
View File

@@ -238,9 +238,9 @@ usrjquota=<file> Appoint specified file and type during mount, so that quota
grpjquota=<file> information can be properly updated during recovery flow,
prjjquota=<file> <quota file>: must be in root directory;
jqfmt=<quota type> <quota type>: [vfsold,vfsv0,vfsv1].
offusrjquota Turn off user journalled quota.
offgrpjquota Turn off group journalled quota.
offprjjquota Turn off project journalled quota.
usrjquota= Turn off user journalled quota.
grpjquota= Turn off group journalled quota.
prjjquota= Turn off project journalled quota.
quota Enable plain user disk quota accounting.
noquota Disable all plain disk quota option.
alloc_mode=%s Adjust block allocation policy, which supports "reuse"

21
Documentation/input/devices/edt-ft5x06.rst
View File

@@ -29,8 +29,25 @@ The driver allows configuration of the touch screen via a set of sysfs files:
For debugging purposes the driver provides a few files in the debug
filesystem (if available in the kernel). In /sys/kernel/debug/edt_ft5x06
you'll find the following files:
filesystem (if available in the kernel). They are located in:
/sys/kernel/debug/i2c/<i2c-bus>/<i2c-device>/
If you don't know the bus and device numbers, you can look them up with this
command:
$ ls -l /sys/bus/i2c/drivers/edt_ft5x06
The dereference of the symlink will contain the needed information. You will
need the last two elements of its path:
0-0038 -> ../../../../devices/platform/soc/fcfee800.i2c/i2c-0/0-0038
So in this case, the location for the debug files is:
/sys/kernel/debug/i2c/i2c-0/0-0038/
There, you'll find the following files:
num_x, num_y:
(readonly) contains the number of sensor fields in X- and

19
Documentation/input/gamepad.rst
View File

@@ -190,8 +190,21 @@ Gamepads report the following events:
Rumble is advertised as FF_RUMBLE.
- Grip buttons:
Many pads include buttons on the rear, usually referred to as either grip or
rear buttons, or paddles. These are often reprogrammable by the firmware to
appear as "normal" buttons, but are sometimes exposed to software too. Some
notable examples of this are the Steam Deck, which has R4, R5, L4, and L5 on
the back; the Xbox Elite pads, which have P1-P4; and the Switch 2 Pro
Controller, which has GL and GR.
For these controllers, BTN_GRIPR and BTN_GRIPR2 should be used for the top
and bottom (if present) right grip button(s), and BTN_GRIPL and BTN_GRIPL2
should be used for the top and bottom (if present) left grip button(s).
- Profile:
Some pads provide a multi-value profile selection switch. An example is the
XBox Adaptive and the XBox Elite 2 controllers. When the active profile is
switched, its newly selected value is emitted as an ABS_PROFILE event.
Some pads provide a multi-value profile selection switch. Examples include
the Xbox Adaptive and the Xbox Elite 2 controllers. When the active profile
is switched, its newly selected value is emitted as an ABS_PROFILE event.

8
Documentation/kbuild/kconfig.rst
View File

@@ -67,12 +67,12 @@ Environment variables for ``*config``:
with its value when saving the configuration, instead of using the
default, ``CONFIG_``.
Environment variables for ``{allyes/allmod/allno/rand}config``:
Environment variables for ``{allyes/allmod/allno/alldef/rand}config``:
``KCONFIG_ALLCONFIG``
The allyesconfig/allmodconfig/allnoconfig/randconfig variants can also
use the environment variable KCONFIG_ALLCONFIG as a flag or a filename
that contains config symbols that the user requires to be set to a
The allyesconfig/allmodconfig/alldefconfig/allnoconfig/randconfig variants
can also use the environment variable KCONFIG_ALLCONFIG as a flag or a
filename that contains config symbols that the user requires to be set to a
specific value. If KCONFIG_ALLCONFIG is used without a filename where
KCONFIG_ALLCONFIG == "" or KCONFIG_ALLCONFIG == "1", ``make *config``
checks for a file named "all{yes/mod/no/def/random}.config"

6
Documentation/netlink/specs/ethtool.yaml
View File

@@ -2342,9 +2342,6 @@ operations:
do: &module-eeprom-get-op
request:
attributes:
- header
reply:
attributes:
- header
- offset
@@ -2352,6 +2349,9 @@ operations:
- page
- bank
- i2c-address
reply:
attributes:
- header
- data
dump: *module-eeprom-get-op
-

4
Documentation/userspace-api/media/rc/rc-protos.rst
View File

@@ -449,6 +449,6 @@ the 32 bits.
xbox-dvd (RC_PROTO_XBOX_DVD)
----------------------------
This protocol is used by XBox DVD Remote, which was made for the original
XBox. There is no in-kernel decoder or encoder for this protocol. The usb
This protocol is used by Xbox DVD Remote, which was made for the original
Xbox. There is no in-kernel decoder or encoder for this protocol. The usb
device decodes the protocol. There is a BPF decoder available in v4l-utils.

71
MAINTAINERS
View File

@@ -6713,7 +6713,7 @@ S: Supported
F: drivers/input/keyboard/dlink-dir685-touchkeys.c
DALLAS/MAXIM DS1685-FAMILY REAL TIME CLOCK
M: Joshua Kinard <kumba@gentoo.org>
M: Joshua Kinard <linux@kumba.dev>
S: Maintained
F: drivers/rtc/rtc-ds1685.c
F: include/linux/rtc/ds1685.h
@@ -11100,7 +11100,7 @@ F: Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt
F: drivers/infiniband/hw/hns/
HISILICON SAS Controller
M: Yihang Li <liyihang9@huawei.com>
M: Yihang Li <liyihang9@h-partners.com>
S: Supported
W: http://www.hisilicon.com
F: Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
@@ -11612,6 +11612,13 @@ S: Maintained
F: Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
F: drivers/i3c/master/i3c-master-cdns.c
I3C DRIVER FOR RENESAS
M: Wolfram Sang <wsa+renesas@sang-engineering.com>
M: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
S: Supported
F: Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
F: drivers/i3c/master/renesas-i3c.c
I3C DRIVER FOR SYNOPSYS DESIGNWARE
S: Orphan
F: Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
@@ -11622,6 +11629,7 @@ M: Alexandre Belloni <alexandre.belloni@bootlin.com>
R: Frank Li <Frank.Li@nxp.com>
L: linux-i3c@lists.infradead.org (moderated for non-subscribers)
S: Maintained
Q: https://patchwork.kernel.org/project/linux-i3c/list/
C: irc://chat.freenode.net/linux-i3c
T: git git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git
F: Documentation/ABI/testing/sysfs-bus-i3c
@@ -13166,11 +13174,9 @@ F: mm/kasan/
F: scripts/Makefile.kasan
KCONFIG
M: Masahiro Yamada <masahiroy@kernel.org>
L: linux-kbuild@vger.kernel.org
S: Maintained
S: Orphan
Q: https://patchwork.kernel.org/project/linux-kbuild/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git kbuild
F: Documentation/kbuild/kconfig*
F: scripts/Kconfig.include
F: scripts/kconfig/
@@ -13235,13 +13241,12 @@ S: Maintained
F: fs/autofs/
KERNEL BUILD + files below scripts/ (unless maintained elsewhere)
M: Masahiro Yamada <masahiroy@kernel.org>
R: Nathan Chancellor <nathan@kernel.org>
R: Nicolas Schier <nicolas@fjasle.eu>
M: Nathan Chancellor <nathan@kernel.org>
M: Nicolas Schier <nicolas@fjasle.eu>
L: linux-kbuild@vger.kernel.org
S: Maintained
S: Odd Fixes
Q: https://patchwork.kernel.org/project/linux-kbuild/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux.git
F: Documentation/kbuild/
F: Makefile
F: scripts/*vmlinux*
@@ -13536,6 +13541,7 @@ F: Documentation/admin-guide/mm/kho.rst
F: Documentation/core-api/kho/*
F: include/linux/kexec_handover.h
F: kernel/kexec_handover.c
F: tools/testing/selftests/kho/
KEYS-ENCRYPTED
M: Mimi Zohar <zohar@linux.ibm.com>
@@ -19733,6 +19739,16 @@ S: Maintained
F: include/linux/delayacct.h
F: kernel/delayacct.c
TASK DELAY MONITORING TOOLS
M: Andrew Morton <akpm@linux-foundation.org>
M: Wang Yaxin <wang.yaxin@zte.com.cn>
M: Fan Yu <fan.yu9@zte.com.cn>
L: linux-kernel@vger.kernel.org
S: Maintained
F: Documentation/accounting/delay-accounting.rst
F: tools/accounting/delaytop.c
F: tools/accounting/getdelays.c
PERFORMANCE EVENTS SUBSYSTEM
M: Peter Zijlstra <peterz@infradead.org>
M: Ingo Molnar <mingo@redhat.com>
@@ -21471,6 +21487,14 @@ S: Maintained
F: Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
F: drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c
RENESAS RZ/V2H(P) RSPI DRIVER
M: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
L: linux-spi@vger.kernel.org
L: linux-renesas-soc@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
F: drivers/spi/spi-rzv2h-rspi.c
RENESAS RZ/V2H(P) USB2PHY PORT RESET DRIVER
M: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
@@ -22032,6 +22056,10 @@ K: \b(?i:rust)\b
RUST [ALLOC]
M: Danilo Krummrich <dakr@kernel.org>
R: Lorenzo Stoakes <lorenzo.stoakes@oracle.com>
R: Vlastimil Babka <vbabka@suse.cz>
R: Liam R. Howlett <Liam.Howlett@oracle.com>
R: Uladzislau Rezki <urezki@gmail.com>
L: rust-for-linux@vger.kernel.org
S: Maintained
T: git https://github.com/Rust-for-Linux/linux.git alloc-next
@@ -23370,6 +23398,7 @@ F: drivers/md/md*
F: drivers/md/raid*
F: include/linux/raid/
F: include/uapi/linux/raid/
F: lib/raid6/
SOLIDRUN CLEARFOG SUPPORT
M: Russell King <linux@armlinux.org.uk>
@@ -23814,6 +23843,12 @@ F: drivers/bus/stm32_etzpc.c
F: drivers/bus/stm32_firewall.c
F: drivers/bus/stm32_rifsc.c
ST STM32 HDP PINCTRL DRIVER
M: Clément Le Goffic <legoffic.clement@gmail.com>
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml
F: drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
ST STM32 I2C/SMBUS DRIVER
M: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
M: Alain Volmat <alain.volmat@foss.st.com>
@@ -23827,6 +23862,14 @@ S: Maintained
F: Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml
F: drivers/memory/stm32_omm.c
ST STM32 PINCTRL DRIVER
M: Antonio Borneo <antonio.borneo@foss.st.com>
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
F: drivers/pinctrl/stm32/
F: include/dt-bindings/pinctrl/stm32-pinfunc.h
X: drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
ST STM32 SPI DRIVER
M: Alain Volmat <alain.volmat@foss.st.com>
L: linux-spi@vger.kernel.org
@@ -25464,6 +25507,13 @@ L: platform-driver-x86@vger.kernel.org
S: Maintained
F: drivers/platform/x86/toshiba-wmi.c
TOUCH OVERLAY
M: Javier Carrasco <javier.carrasco@wolfvision.net>
L: linux-input@vger.kernel.org
S: Maintained
F: drivers/input/touch-overlay.c
F: include/linux/input/touch-overlay.h
TPM DEVICE DRIVER
M: Peter Huewe <peterhuewe@gmx.de>
M: Jarkko Sakkinen <jarkko@kernel.org>
@@ -26420,7 +26470,6 @@ S: Maintained
F: drivers/vfio/platform/
VFIO QAT PCI DRIVER
M: Xin Zeng <xin.zeng@intel.com>
M: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
L: kvm@vger.kernel.org
L: qat-linux@intel.com

15
Makefile
View File

@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 16
PATCHLEVEL = 17
SUBLEVEL = 0
EXTRAVERSION =
EXTRAVERSION = -rc1
NAME = Baby Opossum Posse
# *DOCUMENTATION*
@@ -479,11 +479,17 @@ export rust_common_flags := --edition=2021 \
-Wrust_2018_idioms \
-Wunreachable_pub \
-Wclippy::all \
-Wclippy::as_ptr_cast_mut \
-Wclippy::as_underscore \
-Wclippy::cast_lossless \
-Wclippy::ignored_unit_patterns \
-Wclippy::mut_mut \
-Wclippy::needless_bitwise_bool \
-Aclippy::needless_lifetimes \
-Wclippy::no_mangle_with_rust_abi \
-Wclippy::ptr_as_ptr \
-Wclippy::ptr_cast_constness \
-Wclippy::ref_as_ptr \
-Wclippy::undocumented_unsafe_blocks \
-Wclippy::unnecessary_safety_comment \
-Wclippy::unnecessary_safety_doc \
@@ -543,6 +549,7 @@ LZMA = lzma
LZ4 = lz4
XZ = xz
ZSTD = zstd
TAR = tar
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
-Wbitwise -Wno-return-void -Wno-unknown-attribute $(CF)
@@ -622,7 +629,7 @@ export RUSTC RUSTDOC RUSTFMT RUSTC_OR_CLIPPY_QUIET RUSTC_OR_CLIPPY BINDGEN
export HOSTRUSTC KBUILD_HOSTRUSTFLAGS
export CPP AR NM STRIP OBJCOPY OBJDUMP READELF PAHOLE RESOLVE_BTFIDS LEX YACC AWK INSTALLKERNEL
export PERL PYTHON3 CHECK CHECKFLAGS MAKE UTS_MACHINE HOSTCXX
export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ ZSTD
export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ ZSTD TAR
export KBUILD_HOSTCXXFLAGS KBUILD_HOSTLDFLAGS KBUILD_HOSTLDLIBS KBUILD_PROCMACROLDFLAGS LDFLAGS_MODULE
export KBUILD_USERCFLAGS KBUILD_USERLDFLAGS
@@ -1135,7 +1142,7 @@ KBUILD_USERCFLAGS += $(filter -m32 -m64 --target=%, $(KBUILD_CPPFLAGS) $(KBUILD
KBUILD_USERLDFLAGS += $(filter -m32 -m64 --target=%, $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS))
# userspace programs are linked via the compiler, use the correct linker
ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_LD_IS_LLD),yy)
ifdef CONFIG_CC_IS_CLANG
KBUILD_USERLDFLAGS += --ld-path=$(LD)
endif

11
arch/alpha/kernel/core_marvel.c
View File

@@ -17,6 +17,7 @@
#include <linux/vmalloc.h>
#include <linux/mc146818rtc.h>
#include <linux/rtc.h>
#include <linux/string.h>
#include <linux/module.h>
#include <linux/memblock.h>
@@ -79,10 +80,12 @@ mk_resource_name(int pe, int port, char *str)
{
char tmp[80];
char *name;
sprintf(tmp, "PCI %s PE %d PORT %d", str, pe, port);
name = memblock_alloc_or_panic(strlen(tmp) + 1, SMP_CACHE_BYTES);
strcpy(name, tmp);
size_t sz;
sz = scnprintf(tmp, sizeof(tmp), "PCI %s PE %d PORT %d", str, pe, port);
sz += 1; /* NUL terminator */
name = memblock_alloc_or_panic(sz, SMP_CACHE_BYTES);
strscpy(name, tmp, sz);
return name;
}

9
arch/arm/boot/dts/broadcom/bcm7445.dtsi
View File

@@ -237,7 +237,8 @@
ranges = <0x0 0x0 0x80000>;
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
"brcm,brcmstb-memc-ddr";
reg = <0x2000 0x800>;
};
@@ -259,7 +260,8 @@
ranges = <0x0 0x80000 0x80000>;
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
"brcm,brcmstb-memc-ddr";
reg = <0x2000 0x800>;
};
@@ -281,7 +283,8 @@
ranges = <0x0 0x100000 0x80000>;
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
"brcm,brcmstb-memc-ddr";
reg = <0x2000 0x800>;
};

4
arch/arm/common/sa1111.c
View File

@@ -617,8 +617,8 @@ static int sa1111_setup_gpios(struct sa1111 *sachip)
sachip->gc.direction_input = sa1111_gpio_direction_input;
sachip->gc.direction_output = sa1111_gpio_direction_output;
sachip->gc.get = sa1111_gpio_get;
sachip->gc.set_rv = sa1111_gpio_set;
sachip->gc.set_multiple_rv = sa1111_gpio_set_multiple;
sachip->gc.set = sa1111_gpio_set;
sachip->gc.set_multiple = sa1111_gpio_set_multiple;
sachip->gc.to_irq = sa1111_gpio_to_irq;
sachip->gc.base = -1;
sachip->gc.ngpio = 18;

2
arch/arm/common/scoop.c
View File

@@ -218,7 +218,7 @@ static int scoop_probe(struct platform_device *pdev)
devptr->gpio.label = dev_name(&pdev->dev);
devptr->gpio.base = inf->gpio_base;
devptr->gpio.ngpio = 12; /* PA11 = 0, PA12 = 1, etc. up to PA22 = 11 */
devptr->gpio.set_rv = scoop_gpio_set;
devptr->gpio.set = scoop_gpio_set;
devptr->gpio.get = scoop_gpio_get;
devptr->gpio.direction_input = scoop_gpio_direction_input;
devptr->gpio.direction_output = scoop_gpio_direction_output;

160
arch/arm/include/asm/cti.h
View File

@@ -1,160 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASMARM_CTI_H
#define __ASMARM_CTI_H
#include <asm/io.h>
#include <asm/hardware/coresight.h>
/* The registers' definition is from section 3.2 of
* Embedded Cross Trigger Revision: r0p0
*/
#define CTICONTROL 0x000
#define CTISTATUS 0x004
#define CTILOCK 0x008
#define CTIPROTECTION 0x00C
#define CTIINTACK 0x010
#define CTIAPPSET 0x014
#define CTIAPPCLEAR 0x018
#define CTIAPPPULSE 0x01c
#define CTIINEN 0x020
#define CTIOUTEN 0x0A0
#define CTITRIGINSTATUS 0x130
#define CTITRIGOUTSTATUS 0x134
#define CTICHINSTATUS 0x138
#define CTICHOUTSTATUS 0x13c
#define CTIPERIPHID0 0xFE0
#define CTIPERIPHID1 0xFE4
#define CTIPERIPHID2 0xFE8
#define CTIPERIPHID3 0xFEC
#define CTIPCELLID0 0xFF0
#define CTIPCELLID1 0xFF4
#define CTIPCELLID2 0xFF8
#define CTIPCELLID3 0xFFC
/* The below are from section 3.6.4 of
* CoreSight v1.0 Architecture Specification
*/
#define LOCKACCESS 0xFB0
#define LOCKSTATUS 0xFB4
/**
* struct cti - cross trigger interface struct
* @base: mapped virtual address for the cti base
* @irq: irq number for the cti
* @trig_out_for_irq: triger out number which will cause
* the @irq happen
*
* cti struct used to operate cti registers.
*/
struct cti {
void __iomem *base;
int irq;
int trig_out_for_irq;
};
/**
* cti_init - initialize the cti instance
* @cti: cti instance
* @base: mapped virtual address for the cti base
* @irq: irq number for the cti
* @trig_out: triger out number which will cause
* the @irq happen
*
* called by machine code to pass the board dependent
* @base, @irq and @trig_out to cti.
*/
static inline void cti_init(struct cti *cti,
void __iomem *base, int irq, int trig_out)
{
cti->base = base;
cti->irq = irq;
cti->trig_out_for_irq = trig_out;
}
/**
* cti_map_trigger - use the @chan to map @trig_in to @trig_out
* @cti: cti instance
* @trig_in: trigger in number
* @trig_out: trigger out number
* @channel: channel number
*
* This function maps one trigger in of @trig_in to one trigger
* out of @trig_out using the channel @chan.
*/
static inline void cti_map_trigger(struct cti *cti,
int trig_in, int trig_out, int chan)
{
void __iomem *base = cti->base;
unsigned long val;
val = __raw_readl(base + CTIINEN + trig_in * 4);
val |= BIT(chan);
__raw_writel(val, base + CTIINEN + trig_in * 4);
val = __raw_readl(base + CTIOUTEN + trig_out * 4);
val |= BIT(chan);
__raw_writel(val, base + CTIOUTEN + trig_out * 4);
}
/**
* cti_enable - enable the cti module
* @cti: cti instance
*
* enable the cti module
*/
static inline void cti_enable(struct cti *cti)
{
__raw_writel(0x1, cti->base + CTICONTROL);
}
/**
* cti_disable - disable the cti module
* @cti: cti instance
*
* enable the cti module
*/
static inline void cti_disable(struct cti *cti)
{
__raw_writel(0, cti->base + CTICONTROL);
}
/**
* cti_irq_ack - clear the cti irq
* @cti: cti instance
*
* clear the cti irq
*/
static inline void cti_irq_ack(struct cti *cti)
{
void __iomem *base = cti->base;
unsigned long val;
val = __raw_readl(base + CTIINTACK);
val |= BIT(cti->trig_out_for_irq);
__raw_writel(val, base + CTIINTACK);
}
/**
* cti_unlock - unlock cti module
* @cti: cti instance
*
* unlock the cti module, or else any writes to the cti
* module is not allowed.
*/
static inline void cti_unlock(struct cti *cti)
{
__raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
}
/**
* cti_lock - lock cti module
* @cti: cti instance
*
* lock the cti module, so any writes to the cti
* module will be not allowed.
*/
static inline void cti_lock(struct cti *cti)
{
__raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
}
#endif

2
arch/arm/kernel/setup.c
View File

@@ -1004,7 +1004,7 @@ static void __init reserve_crashkernel(void)
total_mem = get_total_mem();
ret = parse_crashkernel(boot_command_line, total_mem,
&crash_size, &crash_base,
NULL, NULL);
NULL, NULL, NULL);
/* invalid value specified or crashkernel=0 */
if (ret || !crash_size)
return;

2
arch/arm/mach-s3c/gpio-samsung.c
View File

@@ -517,7 +517,7 @@ static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
if (!gc->direction_output)
gc->direction_output = samsung_gpiolib_2bit_output;
if (!gc->set)
gc->set_rv = samsung_gpiolib_set;
gc->set = samsung_gpiolib_set;
if (!gc->get)
gc->get = samsung_gpiolib_get;

2
arch/arm/mach-sa1100/assabet.c
View File

@@ -80,7 +80,7 @@ void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
{
unsigned long m = mask, v = val;
assabet_bcr_gc->set_multiple_rv(assabet_bcr_gc, &m, &v);
assabet_bcr_gc->set_multiple(assabet_bcr_gc, &m, &v);
}
EXPORT_SYMBOL(ASSABET_BCR_frob);

2
arch/arm/mach-sa1100/neponset.c
View File

@@ -126,7 +126,7 @@ void neponset_ncr_frob(unsigned int mask, unsigned int val)
unsigned long m = mask, v = val;
if (nep)
n->gpio[0]->set_multiple_rv(n->gpio[0], &m, &v);
n->gpio[0]->set_multiple(n->gpio[0], &m, &v);
else
WARN(1, "nep unset\n");
}

2
arch/arm/plat-orion/gpio.c
View File

@@ -540,7 +540,7 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
ochip->chip.direction_input = orion_gpio_direction_input;
ochip->chip.get = orion_gpio_get;
ochip->chip.direction_output = orion_gpio_direction_output;
ochip->chip.set_rv = orion_gpio_set;
ochip->chip.set = orion_gpio_set;
ochip->chip.to_irq = orion_gpio_to_irq;
ochip->chip.base = gpio_base;
ochip->chip.ngpio = ngpio;

1
arch/arm64/Kconfig.platforms
View File

@@ -333,7 +333,6 @@ config ARCH_STM32
bool "STMicroelectronics STM32 SoC Family"
select GPIOLIB
select PINCTRL
select PINCTRL_STM32MP257
select ARM_SMC_MBOX
select ARM_SCMI_PROTOCOL
select REGULATOR

25
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@@ -1430,6 +1430,31 @@
status = "disabled";
};
ufshci: ufshci@11270000 {
compatible = "mediatek,mt8195-ufshci";
reg = <0 0x11270000 0 0x2300>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&ufsphy>;
clocks = <&infracfg_ao CLK_INFRA_AO_AES_UFSFDE>,
<&infracfg_ao CLK_INFRA_AO_AES>,
<&infracfg_ao CLK_INFRA_AO_UFS_TICK>,
<&infracfg_ao CLK_INFRA_AO_UNIPRO_SYS>,
<&infracfg_ao CLK_INFRA_AO_UNIPRO_TICK>,
<&infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B>,
<&infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL>,
<&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>;
clock-names = "ufs", "ufs_aes", "ufs_tick",
"unipro_sysclk", "unipro_tick",
"unipro_mp_bclk", "ufs_tx_symbol",
"ufs_mem_sub";
freq-table-hz = <0 0>, <0 0>, <0 0>,
<0 0>, <0 0>, <0 0>,
<0 0>, <0 0>;
mediatek,ufs-disable-mcq;
status = "disabled";
};
lvts_mcu: thermal-sensor@11278000 {
compatible = "mediatek,mt8195-lvts-mcu";
reg = <0 0x11278000 0 0x1000>;

3
arch/arm64/boot/dts/nvidia/tegra264.dtsi
View File

@@ -11,7 +11,6 @@
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
numa-node-id = <0>;
reserved-memory {
#address-cells = <2>;
@@ -341,7 +340,6 @@
status = "okay";
enable-method = "psci";
numa-node-id = <0>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@@ -358,7 +356,6 @@
status = "okay";
enable-method = "psci";
numa-node-id = <0>;
i-cache-size = <65536>;
i-cache-line-size = <64>;

33
arch/arm64/include/asm/asm-bug.h
View File

@@ -21,16 +21,21 @@
#endif
#ifdef CONFIG_GENERIC_BUG
#define __BUG_ENTRY(flags) \
#define __BUG_ENTRY_START \
.pushsection __bug_table,"aw"; \
.align 2; \
14470: .long 14471f - .; \
_BUGVERBOSE_LOCATION(__FILE__, __LINE__) \
.short flags; \
#define __BUG_ENTRY_END \
.align 2; \
.popsection; \
14471:
#define __BUG_ENTRY(flags) \
__BUG_ENTRY_START \
_BUGVERBOSE_LOCATION(__FILE__, __LINE__) \
.short flags; \
__BUG_ENTRY_END
#else
#define __BUG_ENTRY(flags)
#endif
@@ -41,4 +46,24 @@ _BUGVERBOSE_LOCATION(__FILE__, __LINE__) \
#define ASM_BUG() ASM_BUG_FLAGS(0)
#ifdef CONFIG_DEBUG_BUGVERBOSE
#define __BUG_LOCATION_STRING(file, line) \
".long " file "- .;" \
".short " line ";"
#else
#define __BUG_LOCATION_STRING(file, line)
#endif
#define __BUG_ENTRY_STRING(file, line, flags) \
__stringify(__BUG_ENTRY_START) \
__BUG_LOCATION_STRING(file, line) \
".short " flags ";" \
__stringify(__BUG_ENTRY_END)
#define ARCH_WARN_ASM(file, line, flags, size) \
__BUG_ENTRY_STRING(file, line, flags) \
__stringify(brk BUG_BRK_IMM)
#define ARCH_WARN_REACHABLE
#endif /* __ASM_ASM_BUG_H */

2
arch/arm64/mm/init.c
View File

@@ -106,7 +106,7 @@ static void __init arch_reserve_crashkernel(void)
ret = parse_crashkernel(boot_command_line, memblock_phys_mem_size(),
&crash_size, &crash_base,
&low_size, &high);
&low_size, NULL, &high);
if (ret)
return;

4
arch/arm64/mm/mmu.c
View File

@@ -721,7 +721,7 @@ void mark_rodata_ro(void)
static void __init declare_vma(struct vm_struct *vma,
void *va_start, void *va_end,
vm_flags_t vm_flags)
unsigned long vm_flags)
{
phys_addr_t pa_start = __pa_symbol(va_start);
unsigned long size = va_end - va_start;
@@ -1528,7 +1528,7 @@ early_initcall(prevent_bootmem_remove_init);
pte_t modify_prot_start_ptes(struct vm_area_struct *vma, unsigned long addr,
pte_t *ptep, unsigned int nr)
{
pte_t pte = get_and_clear_full_ptes(vma->vm_mm, addr, ptep, nr, /* full = */ 0);
pte_t pte = get_and_clear_ptes(vma->vm_mm, addr, ptep, nr);
if (alternative_has_cap_unlikely(ARM64_WORKAROUND_2645198)) {
/*

9
arch/loongarch/boot/dts/loongson-2k0500-ref.dts
View File

@@ -41,6 +41,15 @@
};
};
&apbdma3 {
status = "okay";
};
&mmc0 {
status = "okay";
bus-width = <4>;
};
&gmac0 {
status = "okay";

28
arch/loongarch/boot/dts/loongson-2k0500.dtsi
View File

@@ -104,7 +104,7 @@
status = "disabled";
};
dma-controller@1fe10c20 {
apbdma2: dma-controller@1fe10c20 {
compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
reg = <0 0x1fe10c20 0 0x8>;
interrupt-parent = <&eiointc>;
@@ -114,7 +114,7 @@
status = "disabled";
};
dma-controller@1fe10c30 {
apbdma3: dma-controller@1fe10c30 {
compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
reg = <0 0x1fe10c30 0 0x8>;
interrupt-parent = <&eiointc>;
@@ -437,6 +437,30 @@
status = "disabled";
};
mmc0: mmc@1ff64000 {
compatible = "loongson,ls2k0500-mmc";
reg = <0 0x1ff64000 0 0x2000>,
<0 0x1fe10100 0 0x4>;
interrupt-parent = <&eiointc>;
interrupts = <57>;
dmas = <&apbdma3 0>;
dma-names = "rx-tx";
clocks = <&clk LOONGSON2_APB_CLK>;
status = "disabled";
};
mmc@1ff66000 {
compatible = "loongson,ls2k0500-mmc";
reg = <0 0x1ff66000 0 0x2000>,
<0 0x1fe10100 0 0x4>;
interrupt-parent = <&eiointc>;
interrupts = <58>;
dmas = <&apbdma2 0>;
dma-names = "rx-tx";
clocks = <&clk LOONGSON2_APB_CLK>;
status = "disabled";
};
pmc: power-management@1ff6c000 {
compatible = "loongson,ls2k0500-pmc", "syscon";
reg = <0x0 0x1ff6c000 0x0 0x58>;

13
arch/loongarch/boot/dts/loongson-2k1000-ref.dts
View File

@@ -48,6 +48,19 @@
};
};
&apbdma1 {
status = "okay";
};
&mmc {
status = "okay";
pinctrl-0 = <&sdio_pins_default>;
pinctrl-names = "default";
bus-width = <4>;
cd-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
};
&gmac0 {
status = "okay";

24
arch/loongarch/boot/dts/loongson-2k1000.dtsi
View File

@@ -187,14 +187,14 @@
<26 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<0 IRQ_TYPE_NONE>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_NONE>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
@@ -209,13 +209,13 @@
<27 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>,
<>,
<0 IRQ_TYPE_NONE>,
<27 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>,
<>,
<>,
<0 IRQ_TYPE_NONE>,
<0 IRQ_TYPE_NONE>,
<27 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>,
@@ -256,7 +256,7 @@
status = "disabled";
};
dma-controller@1fe00c10 {
apbdma1: dma-controller@1fe00c10 {
compatible = "loongson,ls2k1000-apbdma";
reg = <0x0 0x1fe00c10 0x0 0x8>;
interrupt-parent = <&liointc1>;
@@ -405,6 +405,18 @@
status = "disabled";
};
mmc: mmc@1fe2c000 {
compatible = "loongson,ls2k1000-mmc";
reg = <0 0x1fe2c000 0 0x68>,
<0 0x1fe00438 0 0x8>;
interrupt-parent = <&liointc0>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LOONGSON2_APB_CLK>;
dmas = <&apbdma1 0>;
dma-names = "rx-tx";
status = "disabled";
};
spi0: spi@1fff0220 {
compatible = "loongson,ls2k1000-spi";
reg = <0x0 0x1fff0220 0x0 0x10>;

10
arch/loongarch/boot/dts/loongson-2k2000-ref.dts
View File

@@ -39,6 +39,16 @@
};
};
&emmc {
status = "okay";
bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
no-sd;
no-sdio;
};
&sata {
status = "okay";
};

18
arch/loongarch/boot/dts/loongson-2k2000.dtsi
View File

@@ -259,6 +259,24 @@
status = "disabled";
};
emmc: mmc@79990000 {
compatible = "loongson,ls2k2000-mmc";
reg = <0x0 0x79990000 0x0 0x1000>;
interrupt-parent = <&pic>;
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LOONGSON2_EMMC_CLK>;
status = "disabled";
};
mmc@79991000 {
compatible = "loongson,ls2k2000-mmc";
reg = <0x0 0x79991000 0x0 0x1000>;
interrupt-parent = <&pic>;
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LOONGSON2_EMMC_CLK>;
status = "disabled";
};
pcie@1a000000 {
compatible = "loongson,ls2k-pci";
reg = <0x0 0x1a000000 0x0 0x02000000>,

3
arch/loongarch/include/asm/inst.h
View File

@@ -497,6 +497,7 @@ void arch_simulate_insn(union loongarch_instruction insn, struct pt_regs *regs);
int larch_insn_read(void *addr, u32 *insnp);
int larch_insn_write(void *addr, u32 insn);
int larch_insn_patch_text(void *addr, u32 insn);
int larch_insn_text_copy(void *dst, void *src, size_t len);
u32 larch_insn_gen_nop(void);
u32 larch_insn_gen_b(unsigned long pc, unsigned long dest);
@@ -510,6 +511,8 @@ u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
u32 larch_insn_gen_beq(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
u32 larch_insn_gen_bne(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
static inline bool signed_imm_check(long val, unsigned int bit)

7
arch/loongarch/include/asm/loongarch.h
View File

@@ -451,6 +451,13 @@
#define LOONGARCH_CSR_KS6 0x36
#define LOONGARCH_CSR_KS7 0x37
#define LOONGARCH_CSR_KS8 0x38
#define LOONGARCH_CSR_KS9 0x39
#define LOONGARCH_CSR_KS10 0x3a
#define LOONGARCH_CSR_KS11 0x3b
#define LOONGARCH_CSR_KS12 0x3c
#define LOONGARCH_CSR_KS13 0x3d
#define LOONGARCH_CSR_KS14 0x3e
#define LOONGARCH_CSR_KS15 0x3f
/* Exception allocated KS0, KS1 and KS2 statically */
#define EXCEPTION_KS0 LOONGARCH_CSR_KS0

13
arch/loongarch/kernel/env.c
View File

@@ -39,16 +39,19 @@ void __init init_environ(void)
static int __init init_cpu_fullname(void)
{
struct device_node *root;
int cpu, ret;
char *model;
char *cpuname;
const char *model;
struct device_node *root;
/* Parsing cpuname from DTS model property */
root = of_find_node_by_path("/");
ret = of_property_read_string(root, "model", (const char **)&model);
ret = of_property_read_string(root, "model", &model);
if (ret == 0) {
cpuname = kstrdup(model, GFP_KERNEL);
loongson_sysconf.cpuname = strsep(&cpuname, " ");
}
of_node_put(root);
if (ret == 0)
loongson_sysconf.cpuname = strsep(&model, " ");
if (loongson_sysconf.cpuname && !strncmp(loongson_sysconf.cpuname, "Loongson", 8)) {
for (cpu = 0; cpu < NR_CPUS; cpu++)

74
arch/loongarch/kernel/inst.c
View File

@@ -4,6 +4,8 @@
*/
#include <linux/sizes.h>
#include <linux/uaccess.h>
#include <linux/set_memory.h>
#include <linux/stop_machine.h>
#include <asm/cacheflush.h>
#include <asm/inst.h>
@@ -218,6 +220,50 @@ int larch_insn_patch_text(void *addr, u32 insn)
return ret;
}
struct insn_copy {
void *dst;
void *src;
size_t len;
unsigned int cpu;
};
static int text_copy_cb(void *data)
{
int ret = 0;
struct insn_copy *copy = data;
if (smp_processor_id() == copy->cpu) {
ret = copy_to_kernel_nofault(copy->dst, copy->src, copy->len);
if (ret)
pr_err("%s: operation failed\n", __func__);
}
flush_icache_range((unsigned long)copy->dst, (unsigned long)copy->dst + copy->len);
return ret;
}
int larch_insn_text_copy(void *dst, void *src, size_t len)
{
int ret = 0;
size_t start, end;
struct insn_copy copy = {
.dst = dst,
.src = src,
.len = len,
.cpu = smp_processor_id(),
};
start = round_down((size_t)dst, PAGE_SIZE);
end = round_up((size_t)dst + len, PAGE_SIZE);
set_memory_rw(start, (end - start) / PAGE_SIZE);
ret = stop_machine(text_copy_cb, &copy, cpu_online_mask);
set_memory_rox(start, (end - start) / PAGE_SIZE);
return ret;
}
u32 larch_insn_gen_nop(void)
{
return INSN_NOP;
@@ -323,6 +369,34 @@ u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
return insn.word;
}
u32 larch_insn_gen_beq(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
{
union loongarch_instruction insn;
if ((imm & 3) || imm < -SZ_128K || imm >= SZ_128K) {
pr_warn("The generated beq instruction is out of range.\n");
return INSN_BREAK;
}
emit_beq(&insn, rj, rd, imm >> 2);
return insn.word;
}
u32 larch_insn_gen_bne(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
{
union loongarch_instruction insn;
if ((imm & 3) || imm < -SZ_128K || imm >= SZ_128K) {
pr_warn("The generated bne instruction is out of range.\n");
return INSN_BREAK;
}
emit_bne(&insn, rj, rd, imm >> 2);
return insn.word;
}
u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
{
union loongarch_instruction insn;

2
arch/loongarch/kernel/relocate_kernel.S
View File

@@ -109,4 +109,4 @@ SYM_CODE_END(kexec_smp_wait)
relocate_new_kernel_end:
.section ".data"
SYM_DATA(relocate_new_kernel_size, .long relocate_new_kernel_end - relocate_new_kernel)
SYM_DATA(relocate_new_kernel_size, .quad relocate_new_kernel_end - relocate_new_kernel)

20
arch/loongarch/kernel/setup.c
View File

@@ -191,6 +191,16 @@ static int __init early_parse_mem(char *p)
return -EINVAL;
}
start = 0;
size = memparse(p, &p);
if (*p == '@') /* Every mem=... should contain '@' */
start = memparse(p + 1, &p);
else { /* Only one mem=... is allowed if no '@' */
usermem = 1;
memblock_enforce_memory_limit(size);
return 0;
}
/*
* If a user specifies memory size, we
* blow away any automatically generated
@@ -201,14 +211,6 @@ static int __init early_parse_mem(char *p)
memblock_remove(memblock_start_of_DRAM(),
memblock_end_of_DRAM() - memblock_start_of_DRAM());
}
start = 0;
size = memparse(p, &p);
if (*p == '@')
start = memparse(p + 1, &p);
else {
pr_err("Invalid format!\n");
return -EINVAL;
}
if (!IS_ENABLED(CONFIG_NUMA))
memblock_add(start, size);
@@ -265,7 +267,7 @@ static void __init arch_reserve_crashkernel(void)
return;
ret = parse_crashkernel(boot_command_line, memblock_phys_mem_size(),
&crash_size, &crash_base, &low_size, &high);
&crash_size, &crash_base, &low_size, NULL, &high);
if (ret)
return;

2
arch/loongarch/kernel/unwind_orc.c
View File

@@ -508,7 +508,7 @@ bool unwind_next_frame(struct unwind_state *state)
state->pc = bt_address(pc);
if (!state->pc) {
pr_err("cannot find unwind pc at %pK\n", (void *)pc);
pr_err("cannot find unwind pc at %p\n", (void *)pc);
goto err;
}

701
arch/loongarch/net/bpf_jit.c
View File

@@ -4,13 +4,20 @@
*
* Copyright (C) 2022 Loongson Technology Corporation Limited
*/
#include <linux/memory.h>
#include "bpf_jit.h"
#define REG_TCC LOONGARCH_GPR_A6
#define TCC_SAVED LOONGARCH_GPR_S5
#define LOONGARCH_MAX_REG_ARGS 8
#define SAVE_RA BIT(0)
#define SAVE_TCC BIT(1)
#define LOONGARCH_LONG_JUMP_NINSNS 5
#define LOONGARCH_LONG_JUMP_NBYTES (LOONGARCH_LONG_JUMP_NINSNS * 4)
#define LOONGARCH_FENTRY_NINSNS 2
#define LOONGARCH_FENTRY_NBYTES (LOONGARCH_FENTRY_NINSNS * 4)
#define LOONGARCH_BPF_FENTRY_NBYTES (LOONGARCH_LONG_JUMP_NINSNS * 4)
#define REG_TCC LOONGARCH_GPR_A6
#define BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack) (round_up(stack, 16) - 80)
static const int regmap[] = {
/* return value from in-kernel function, and exit value for eBPF program */
@@ -32,32 +39,57 @@ static const int regmap[] = {
[BPF_REG_AX] = LOONGARCH_GPR_T0,
};
static void mark_call(struct jit_ctx *ctx)
static void prepare_bpf_tail_call_cnt(struct jit_ctx *ctx, int *store_offset)
{
ctx->flags |= SAVE_RA;
}
const struct bpf_prog *prog = ctx->prog;
const bool is_main_prog = !bpf_is_subprog(prog);
static void mark_tail_call(struct jit_ctx *ctx)
{
ctx->flags |= SAVE_TCC;
}
if (is_main_prog) {
/*
* LOONGARCH_GPR_T3 = MAX_TAIL_CALL_CNT
* if (REG_TCC > T3 )
* std REG_TCC -> LOONGARCH_GPR_SP + store_offset
* else
* std REG_TCC -> LOONGARCH_GPR_SP + store_offset
* REG_TCC = LOONGARCH_GPR_SP + store_offset
*
* std REG_TCC -> LOONGARCH_GPR_SP + store_offset
*
* The purpose of this code is to first push the TCC into stack,
* and then push the address of TCC into stack.
* In cases where bpf2bpf and tailcall are used in combination,
* the value in REG_TCC may be a count or an address,
* these two cases need to be judged and handled separately.
*/
emit_insn(ctx, addid, LOONGARCH_GPR_T3, LOONGARCH_GPR_ZERO, MAX_TAIL_CALL_CNT);
*store_offset -= sizeof(long);
static bool seen_call(struct jit_ctx *ctx)
{
return (ctx->flags & SAVE_RA);
}
emit_cond_jmp(ctx, BPF_JGT, REG_TCC, LOONGARCH_GPR_T3, 4);
static bool seen_tail_call(struct jit_ctx *ctx)
{
return (ctx->flags & SAVE_TCC);
}
/*
* If REG_TCC < MAX_TAIL_CALL_CNT, the value in REG_TCC is a count,
* push tcc into stack
*/
emit_insn(ctx, std, REG_TCC, LOONGARCH_GPR_SP, *store_offset);
static u8 tail_call_reg(struct jit_ctx *ctx)
{
if (seen_call(ctx))
return TCC_SAVED;
/* Push the address of TCC into the REG_TCC */
emit_insn(ctx, addid, REG_TCC, LOONGARCH_GPR_SP, *store_offset);
return REG_TCC;
emit_uncond_jmp(ctx, 2);
/*
* If REG_TCC > MAX_TAIL_CALL_CNT, the value in REG_TCC is an address,
* push tcc_ptr into stack
*/
emit_insn(ctx, std, REG_TCC, LOONGARCH_GPR_SP, *store_offset);
} else {
*store_offset -= sizeof(long);
emit_insn(ctx, std, REG_TCC, LOONGARCH_GPR_SP, *store_offset);
}
/* Push tcc_ptr into stack */
*store_offset -= sizeof(long);
emit_insn(ctx, std, REG_TCC, LOONGARCH_GPR_SP, *store_offset);
}
/*
@@ -80,6 +112,10 @@ static u8 tail_call_reg(struct jit_ctx *ctx)
* | $s4 |
* +-------------------------+
* | $s5 |
* +-------------------------+
* | tcc |
* +-------------------------+
* | tcc_ptr |
* +-------------------------+ <--BPF_REG_FP
* | prog->aux->stack_depth |
* | (optional) |
@@ -88,22 +124,32 @@ static u8 tail_call_reg(struct jit_ctx *ctx)
*/
static void build_prologue(struct jit_ctx *ctx)
{
int stack_adjust = 0, store_offset, bpf_stack_adjust;
int i, stack_adjust = 0, store_offset, bpf_stack_adjust;
const struct bpf_prog *prog = ctx->prog;
const bool is_main_prog = !bpf_is_subprog(prog);
bpf_stack_adjust = round_up(ctx->prog->aux->stack_depth, 16);
/* To store ra, fp, s0, s1, s2, s3, s4 and s5. */
/* To store ra, fp, s0, s1, s2, s3, s4, s5 */
stack_adjust += sizeof(long) * 8;
/* To store tcc and tcc_ptr */
stack_adjust += sizeof(long) * 2;
stack_adjust = round_up(stack_adjust, 16);
stack_adjust += bpf_stack_adjust;
/* Reserve space for the move_imm + jirl instruction */
for (i = 0; i < LOONGARCH_LONG_JUMP_NINSNS; i++)
emit_insn(ctx, nop);
/*
* First instruction initializes the tail call count (TCC).
* On tail call we skip this instruction, and the TCC is
* passed in REG_TCC from the caller.
* First instruction initializes the tail call count (TCC)
* register to zero. On tail call we skip this instruction,
* and the TCC is passed in REG_TCC from the caller.
*/
emit_insn(ctx, addid, REG_TCC, LOONGARCH_GPR_ZERO, MAX_TAIL_CALL_CNT);
if (is_main_prog)
emit_insn(ctx, addid, REG_TCC, LOONGARCH_GPR_ZERO, 0);
emit_insn(ctx, addid, LOONGARCH_GPR_SP, LOONGARCH_GPR_SP, -stack_adjust);
@@ -131,20 +177,13 @@ static void build_prologue(struct jit_ctx *ctx)
store_offset -= sizeof(long);
emit_insn(ctx, std, LOONGARCH_GPR_S5, LOONGARCH_GPR_SP, store_offset);
prepare_bpf_tail_call_cnt(ctx, &store_offset);
emit_insn(ctx, addid, LOONGARCH_GPR_FP, LOONGARCH_GPR_SP, stack_adjust);
if (bpf_stack_adjust)
emit_insn(ctx, addid, regmap[BPF_REG_FP], LOONGARCH_GPR_SP, bpf_stack_adjust);
/*
* Program contains calls and tail calls, so REG_TCC need
* to be saved across calls.
*/
if (seen_tail_call(ctx) && seen_call(ctx))
move_reg(ctx, TCC_SAVED, REG_TCC);
else
emit_insn(ctx, nop);
ctx->stack_size = stack_adjust;
}
@@ -177,6 +216,16 @@ static void __build_epilogue(struct jit_ctx *ctx, bool is_tail_call)
load_offset -= sizeof(long);
emit_insn(ctx, ldd, LOONGARCH_GPR_S5, LOONGARCH_GPR_SP, load_offset);
/*
* When push into the stack, follow the order of tcc then tcc_ptr.
* When pop from the stack, first pop tcc_ptr then followed by tcc.
*/
load_offset -= 2 * sizeof(long);
emit_insn(ctx, ldd, REG_TCC, LOONGARCH_GPR_SP, load_offset);
load_offset += sizeof(long);
emit_insn(ctx, ldd, REG_TCC, LOONGARCH_GPR_SP, load_offset);
emit_insn(ctx, addid, LOONGARCH_GPR_SP, LOONGARCH_GPR_SP, stack_adjust);
if (!is_tail_call) {
@@ -189,7 +238,7 @@ static void __build_epilogue(struct jit_ctx *ctx, bool is_tail_call)
* Call the next bpf prog and skip the first instruction
* of TCC initialization.
*/
emit_insn(ctx, jirl, LOONGARCH_GPR_ZERO, LOONGARCH_GPR_T3, 1);
emit_insn(ctx, jirl, LOONGARCH_GPR_ZERO, LOONGARCH_GPR_T3, 6);
}
}
@@ -208,12 +257,10 @@ bool bpf_jit_supports_far_kfunc_call(void)
return true;
}
/* initialized on the first pass of build_body() */
static int out_offset = -1;
static int emit_bpf_tail_call(struct jit_ctx *ctx)
static int emit_bpf_tail_call(struct jit_ctx *ctx, int insn)
{
int off;
u8 tcc = tail_call_reg(ctx);
int off, tc_ninsn = 0;
int tcc_ptr_off = BPF_TAIL_CALL_CNT_PTR_STACK_OFF(ctx->stack_size);
u8 a1 = LOONGARCH_GPR_A1;
u8 a2 = LOONGARCH_GPR_A2;
u8 t1 = LOONGARCH_GPR_T1;
@@ -222,7 +269,7 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
const int idx0 = ctx->idx;
#define cur_offset (ctx->idx - idx0)
#define jmp_offset (out_offset - (cur_offset))
#define jmp_offset (tc_ninsn - (cur_offset))
/*
* a0: &ctx
@@ -232,6 +279,7 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
* if (index >= array->map.max_entries)
* goto out;
*/
tc_ninsn = insn ? ctx->offset[insn+1] - ctx->offset[insn] : ctx->offset[0];
off = offsetof(struct bpf_array, map.max_entries);
emit_insn(ctx, ldwu, t1, a1, off);
/* bgeu $a2, $t1, jmp_offset */
@@ -239,11 +287,15 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
goto toofar;
/*
* if (--TCC < 0)
* goto out;
* if ((*tcc_ptr)++ >= MAX_TAIL_CALL_CNT)
* goto out;
*/
emit_insn(ctx, addid, REG_TCC, tcc, -1);
if (emit_tailcall_jmp(ctx, BPF_JSLT, REG_TCC, LOONGARCH_GPR_ZERO, jmp_offset) < 0)
emit_insn(ctx, ldd, REG_TCC, LOONGARCH_GPR_SP, tcc_ptr_off);
emit_insn(ctx, ldd, t3, REG_TCC, 0);
emit_insn(ctx, addid, t3, t3, 1);
emit_insn(ctx, std, t3, REG_TCC, 0);
emit_insn(ctx, addid, t2, LOONGARCH_GPR_ZERO, MAX_TAIL_CALL_CNT);
if (emit_tailcall_jmp(ctx, BPF_JSGT, t3, t2, jmp_offset) < 0)
goto toofar;
/*
@@ -263,15 +315,6 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
emit_insn(ctx, ldd, t3, t2, off);
__build_epilogue(ctx, true);
/* out: */
if (out_offset == -1)
out_offset = cur_offset;
if (cur_offset != out_offset) {
pr_err_once("tail_call out_offset = %d, expected %d!\n",
cur_offset, out_offset);
return -1;
}
return 0;
toofar:
@@ -463,7 +506,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
u64 func_addr;
bool func_addr_fixed, sign_extend;
int i = insn - ctx->prog->insnsi;
int ret, jmp_offset;
int ret, jmp_offset, tcc_ptr_off;
const u8 code = insn->code;
const u8 cond = BPF_OP(code);
const u8 t1 = LOONGARCH_GPR_T1;
@@ -899,12 +942,16 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
/* function call */
case BPF_JMP | BPF_CALL:
mark_call(ctx);
ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass,
&func_addr, &func_addr_fixed);
if (ret < 0)
return ret;
if (insn->src_reg == BPF_PSEUDO_CALL) {
tcc_ptr_off = BPF_TAIL_CALL_CNT_PTR_STACK_OFF(ctx->stack_size);
emit_insn(ctx, ldd, REG_TCC, LOONGARCH_GPR_SP, tcc_ptr_off);
}
move_addr(ctx, t1, func_addr);
emit_insn(ctx, jirl, LOONGARCH_GPR_RA, t1, 0);
@@ -915,8 +962,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
/* tail call */
case BPF_JMP | BPF_TAIL_CALL:
mark_tail_call(ctx);
if (emit_bpf_tail_call(ctx) < 0)
if (emit_bpf_tail_call(ctx, i) < 0)
return -EINVAL;
break;
@@ -1180,12 +1226,528 @@ static int validate_code(struct jit_ctx *ctx)
return -1;
}
return 0;
}
static int validate_ctx(struct jit_ctx *ctx)
{
if (validate_code(ctx))
return -1;
if (WARN_ON_ONCE(ctx->num_exentries != ctx->prog->aux->num_exentries))
return -1;
return 0;
}
static int emit_jump_and_link(struct jit_ctx *ctx, u8 rd, u64 target)
{
if (!target) {
pr_err("bpf_jit: jump target address is error\n");
return -EFAULT;
}
move_imm(ctx, LOONGARCH_GPR_T1, target, false);
emit_insn(ctx, jirl, rd, LOONGARCH_GPR_T1, 0);
return 0;
}
static int emit_jump_or_nops(void *target, void *ip, u32 *insns, bool is_call)
{
int i;
struct jit_ctx ctx;
ctx.idx = 0;
ctx.image = (union loongarch_instruction *)insns;
if (!target) {
for (i = 0; i < LOONGARCH_LONG_JUMP_NINSNS; i++)
emit_insn((&ctx), nop);
return 0;
}
return emit_jump_and_link(&ctx, is_call ? LOONGARCH_GPR_T0 : LOONGARCH_GPR_ZERO, (u64)target);
}
static int emit_call(struct jit_ctx *ctx, u64 addr)
{
return emit_jump_and_link(ctx, LOONGARCH_GPR_RA, addr);
}
void *bpf_arch_text_copy(void *dst, void *src, size_t len)
{
int ret;
mutex_lock(&text_mutex);
ret = larch_insn_text_copy(dst, src, len);
mutex_unlock(&text_mutex);
return ret ? ERR_PTR(-EINVAL) : dst;
}
int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type poke_type,
void *old_addr, void *new_addr)
{
int ret;
bool is_call = (poke_type == BPF_MOD_CALL);
u32 old_insns[LOONGARCH_LONG_JUMP_NINSNS] = {[0 ... 4] = INSN_NOP};
u32 new_insns[LOONGARCH_LONG_JUMP_NINSNS] = {[0 ... 4] = INSN_NOP};
if (!is_kernel_text((unsigned long)ip) &&
!is_bpf_text_address((unsigned long)ip))
return -ENOTSUPP;
ret = emit_jump_or_nops(old_addr, ip, old_insns, is_call);
if (ret)
return ret;
if (memcmp(ip, old_insns, LOONGARCH_LONG_JUMP_NBYTES))
return -EFAULT;
ret = emit_jump_or_nops(new_addr, ip, new_insns, is_call);
if (ret)
return ret;
mutex_lock(&text_mutex);
if (memcmp(ip, new_insns, LOONGARCH_LONG_JUMP_NBYTES))
ret = larch_insn_text_copy(ip, new_insns, LOONGARCH_LONG_JUMP_NBYTES);
mutex_unlock(&text_mutex);
return ret;
}
int bpf_arch_text_invalidate(void *dst, size_t len)
{
int i;
int ret = 0;
u32 *inst;
inst = kvmalloc(len, GFP_KERNEL);
if (!inst)
return -ENOMEM;
for (i = 0; i < (len / sizeof(u32)); i++)
inst[i] = INSN_BREAK;
mutex_lock(&text_mutex);
if (larch_insn_text_copy(dst, inst, len))
ret = -EINVAL;
mutex_unlock(&text_mutex);
kvfree(inst);
return ret;
}
static void store_args(struct jit_ctx *ctx, int nargs, int args_off)
{
int i;
for (i = 0; i < nargs; i++) {
emit_insn(ctx, std, LOONGARCH_GPR_A0 + i, LOONGARCH_GPR_FP, -args_off);
args_off -= 8;
}
}
static void restore_args(struct jit_ctx *ctx, int nargs, int args_off)
{
int i;
for (i = 0; i < nargs; i++) {
emit_insn(ctx, ldd, LOONGARCH_GPR_A0 + i, LOONGARCH_GPR_FP, -args_off);
args_off -= 8;
}
}
static int invoke_bpf_prog(struct jit_ctx *ctx, struct bpf_tramp_link *l,
int args_off, int retval_off, int run_ctx_off, bool save_ret)
{
int ret;
u32 *branch;
struct bpf_prog *p = l->link.prog;
int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie);
if (l->cookie) {
move_imm(ctx, LOONGARCH_GPR_T1, l->cookie, false);
emit_insn(ctx, std, LOONGARCH_GPR_T1, LOONGARCH_GPR_FP, -run_ctx_off + cookie_off);
} else {
emit_insn(ctx, std, LOONGARCH_GPR_ZERO, LOONGARCH_GPR_FP, -run_ctx_off + cookie_off);
}
/* arg1: prog */
move_imm(ctx, LOONGARCH_GPR_A0, (const s64)p, false);
/* arg2: &run_ctx */
emit_insn(ctx, addid, LOONGARCH_GPR_A1, LOONGARCH_GPR_FP, -run_ctx_off);
ret = emit_call(ctx, (const u64)bpf_trampoline_enter(p));
if (ret)
return ret;
/* store prog start time */
move_reg(ctx, LOONGARCH_GPR_S1, LOONGARCH_GPR_A0);
/*
* if (__bpf_prog_enter(prog) == 0)
* goto skip_exec_of_prog;
*/
branch = (u32 *)ctx->image + ctx->idx;
/* nop reserved for conditional jump */
emit_insn(ctx, nop);
/* arg1: &args_off */
emit_insn(ctx, addid, LOONGARCH_GPR_A0, LOONGARCH_GPR_FP, -args_off);
if (!p->jited)
move_imm(ctx, LOONGARCH_GPR_A1, (const s64)p->insnsi, false);
ret = emit_call(ctx, (const u64)p->bpf_func);
if (ret)
return ret;
if (save_ret) {
emit_insn(ctx, std, LOONGARCH_GPR_A0, LOONGARCH_GPR_FP, -retval_off);
emit_insn(ctx, std, regmap[BPF_REG_0], LOONGARCH_GPR_FP, -(retval_off - 8));
}
/* update branch with beqz */
if (ctx->image) {
int offset = (void *)(&ctx->image[ctx->idx]) - (void *)branch;
*branch = larch_insn_gen_beq(LOONGARCH_GPR_A0, LOONGARCH_GPR_ZERO, offset);
}
/* arg1: prog */
move_imm(ctx, LOONGARCH_GPR_A0, (const s64)p, false);
/* arg2: prog start time */
move_reg(ctx, LOONGARCH_GPR_A1, LOONGARCH_GPR_S1);
/* arg3: &run_ctx */
emit_insn(ctx, addid, LOONGARCH_GPR_A2, LOONGARCH_GPR_FP, -run_ctx_off);
ret = emit_call(ctx, (const u64)bpf_trampoline_exit(p));
return ret;
}
static void invoke_bpf_mod_ret(struct jit_ctx *ctx, struct bpf_tramp_links *tl,
int args_off, int retval_off, int run_ctx_off, u32 **branches)
{
int i;
emit_insn(ctx, std, LOONGARCH_GPR_ZERO, LOONGARCH_GPR_FP, -retval_off);
for (i = 0; i < tl->nr_links; i++) {
invoke_bpf_prog(ctx, tl->links[i], args_off, retval_off, run_ctx_off, true);
emit_insn(ctx, ldd, LOONGARCH_GPR_T1, LOONGARCH_GPR_FP, -retval_off);
branches[i] = (u32 *)ctx->image + ctx->idx;
emit_insn(ctx, nop);
}
}
void *arch_alloc_bpf_trampoline(unsigned int size)
{
return bpf_prog_pack_alloc(size, jit_fill_hole);
}
void arch_free_bpf_trampoline(void *image, unsigned int size)
{
bpf_prog_pack_free(image, size);
}
static int __arch_prepare_bpf_trampoline(struct jit_ctx *ctx, struct bpf_tramp_image *im,
const struct btf_func_model *m, struct bpf_tramp_links *tlinks,
void *func_addr, u32 flags)
{
int i, ret, save_ret;
int stack_size = 0, nargs = 0;
int retval_off, args_off, nargs_off, ip_off, run_ctx_off, sreg_off, tcc_ptr_off;
bool is_struct_ops = flags & BPF_TRAMP_F_INDIRECT;
void *orig_call = func_addr;
struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
u32 **branches = NULL;
if (flags & (BPF_TRAMP_F_ORIG_STACK | BPF_TRAMP_F_SHARE_IPMODIFY))
return -ENOTSUPP;
/*
* FP + 8 [ RA to parent func ] return address to parent
* function
* FP + 0 [ FP of parent func ] frame pointer of parent
* function
* FP - 8 [ T0 to traced func ] return address of traced
* function
* FP - 16 [ FP of traced func ] frame pointer of traced
* function
*
* FP - retval_off [ return value ] BPF_TRAMP_F_CALL_ORIG or
* BPF_TRAMP_F_RET_FENTRY_RET
* [ argN ]
* [ ... ]
* FP - args_off [ arg1 ]
*
* FP - nargs_off [ regs count ]
*
* FP - ip_off [ traced func ] BPF_TRAMP_F_IP_ARG
*
* FP - run_ctx_off [ bpf_tramp_run_ctx ]
*
* FP - sreg_off [ callee saved reg ]
*
* FP - tcc_ptr_off [ tail_call_cnt_ptr ]
*/
if (m->nr_args > LOONGARCH_MAX_REG_ARGS)
return -ENOTSUPP;
if (flags & (BPF_TRAMP_F_ORIG_STACK | BPF_TRAMP_F_SHARE_IPMODIFY))
return -ENOTSUPP;
stack_size = 0;
/* Room of trampoline frame to store return address and frame pointer */
stack_size += 16;
save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
if (save_ret) {
/* Save BPF R0 and A0 */
stack_size += 16;
retval_off = stack_size;
}
/* Room of trampoline frame to store args */
nargs = m->nr_args;
stack_size += nargs * 8;
args_off = stack_size;
/* Room of trampoline frame to store args number */
stack_size += 8;
nargs_off = stack_size;
/* Room of trampoline frame to store ip address */
if (flags & BPF_TRAMP_F_IP_ARG) {
stack_size += 8;
ip_off = stack_size;
}
/* Room of trampoline frame to store struct bpf_tramp_run_ctx */
stack_size += round_up(sizeof(struct bpf_tramp_run_ctx), 8);
run_ctx_off = stack_size;
stack_size += 8;
sreg_off = stack_size;
/* Room of trampoline frame to store tail_call_cnt_ptr */
if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) {
stack_size += 8;
tcc_ptr_off = stack_size;
}
stack_size = round_up(stack_size, 16);
if (is_struct_ops) {
/*
* For the trampoline called directly, just handle
* the frame of trampoline.
*/
emit_insn(ctx, addid, LOONGARCH_GPR_SP, LOONGARCH_GPR_SP, -stack_size);
emit_insn(ctx, std, LOONGARCH_GPR_RA, LOONGARCH_GPR_SP, stack_size - 8);
emit_insn(ctx, std, LOONGARCH_GPR_FP, LOONGARCH_GPR_SP, stack_size - 16);
emit_insn(ctx, addid, LOONGARCH_GPR_FP, LOONGARCH_GPR_SP, stack_size);
} else {
/*
* For the trampoline called from function entry,
* the frame of traced function and the frame of
* trampoline need to be considered.
*/
/* RA and FP for parent function */
emit_insn(ctx, addid, LOONGARCH_GPR_SP, LOONGARCH_GPR_SP, -16);
emit_insn(ctx, std, LOONGARCH_GPR_RA, LOONGARCH_GPR_SP, 8);
emit_insn(ctx, std, LOONGARCH_GPR_FP, LOONGARCH_GPR_SP, 0);
emit_insn(ctx, addid, LOONGARCH_GPR_FP, LOONGARCH_GPR_SP, 16);
/* RA and FP for traced function */
emit_insn(ctx, addid, LOONGARCH_GPR_SP, LOONGARCH_GPR_SP, -stack_size);
emit_insn(ctx, std, LOONGARCH_GPR_T0, LOONGARCH_GPR_SP, stack_size - 8);
emit_insn(ctx, std, LOONGARCH_GPR_FP, LOONGARCH_GPR_SP, stack_size - 16);
emit_insn(ctx, addid, LOONGARCH_GPR_FP, LOONGARCH_GPR_SP, stack_size);
}
if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
emit_insn(ctx, std, REG_TCC, LOONGARCH_GPR_FP, -tcc_ptr_off);
/* callee saved register S1 to pass start time */
emit_insn(ctx, std, LOONGARCH_GPR_S1, LOONGARCH_GPR_FP, -sreg_off);
/* store ip address of the traced function */
if (flags & BPF_TRAMP_F_IP_ARG) {
move_imm(ctx, LOONGARCH_GPR_T1, (const s64)func_addr, false);
emit_insn(ctx, std, LOONGARCH_GPR_T1, LOONGARCH_GPR_FP, -ip_off);
}
/* store nargs number */
move_imm(ctx, LOONGARCH_GPR_T1, nargs, false);
emit_insn(ctx, std, LOONGARCH_GPR_T1, LOONGARCH_GPR_FP, -nargs_off);
store_args(ctx, nargs, args_off);
/* To traced function */
/* Ftrace jump skips 2 NOP instructions */
if (is_kernel_text((unsigned long)orig_call))
orig_call += LOONGARCH_FENTRY_NBYTES;
/* Direct jump skips 5 NOP instructions */
else if (is_bpf_text_address((unsigned long)orig_call))
orig_call += LOONGARCH_BPF_FENTRY_NBYTES;
if (flags & BPF_TRAMP_F_CALL_ORIG) {
move_imm(ctx, LOONGARCH_GPR_A0, (const s64)im, false);
ret = emit_call(ctx, (const u64)__bpf_tramp_enter);
if (ret)
return ret;
}
for (i = 0; i < fentry->nr_links; i++) {
ret = invoke_bpf_prog(ctx, fentry->links[i], args_off, retval_off,
run_ctx_off, flags & BPF_TRAMP_F_RET_FENTRY_RET);
if (ret)
return ret;
}
if (fmod_ret->nr_links) {
branches = kcalloc(fmod_ret->nr_links, sizeof(u32 *), GFP_KERNEL);
if (!branches)
return -ENOMEM;
invoke_bpf_mod_ret(ctx, fmod_ret, args_off, retval_off, run_ctx_off, branches);
}
if (flags & BPF_TRAMP_F_CALL_ORIG) {
restore_args(ctx, m->nr_args, args_off);
if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
emit_insn(ctx, ldd, REG_TCC, LOONGARCH_GPR_FP, -tcc_ptr_off);
ret = emit_call(ctx, (const u64)orig_call);
if (ret)
goto out;
emit_insn(ctx, std, LOONGARCH_GPR_A0, LOONGARCH_GPR_FP, -retval_off);
emit_insn(ctx, std, regmap[BPF_REG_0], LOONGARCH_GPR_FP, -(retval_off - 8));
im->ip_after_call = ctx->ro_image + ctx->idx;
/* Reserve space for the move_imm + jirl instruction */
for (i = 0; i < LOONGARCH_LONG_JUMP_NINSNS; i++)
emit_insn(ctx, nop);
}
for (i = 0; ctx->image && i < fmod_ret->nr_links; i++) {
int offset = (void *)(&ctx->image[ctx->idx]) - (void *)branches[i];
*branches[i] = larch_insn_gen_bne(LOONGARCH_GPR_T1, LOONGARCH_GPR_ZERO, offset);
}
for (i = 0; i < fexit->nr_links; i++) {
ret = invoke_bpf_prog(ctx, fexit->links[i], args_off, retval_off, run_ctx_off, false);
if (ret)
goto out;
}
if (flags & BPF_TRAMP_F_CALL_ORIG) {
im->ip_epilogue = ctx->ro_image + ctx->idx;
move_imm(ctx, LOONGARCH_GPR_A0, (const s64)im, false);
ret = emit_call(ctx, (const u64)__bpf_tramp_exit);
if (ret)
goto out;
}
if (flags & BPF_TRAMP_F_RESTORE_REGS)
restore_args(ctx, m->nr_args, args_off);
if (save_ret) {
emit_insn(ctx, ldd, LOONGARCH_GPR_A0, LOONGARCH_GPR_FP, -retval_off);
emit_insn(ctx, ldd, regmap[BPF_REG_0], LOONGARCH_GPR_FP, -(retval_off - 8));
}
emit_insn(ctx, ldd, LOONGARCH_GPR_S1, LOONGARCH_GPR_FP, -sreg_off);
if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
emit_insn(ctx, ldd, REG_TCC, LOONGARCH_GPR_FP, -tcc_ptr_off);
if (is_struct_ops) {
/* trampoline called directly */
emit_insn(ctx, ldd, LOONGARCH_GPR_RA, LOONGARCH_GPR_SP, stack_size - 8);
emit_insn(ctx, ldd, LOONGARCH_GPR_FP, LOONGARCH_GPR_SP, stack_size - 16);
emit_insn(ctx, addid, LOONGARCH_GPR_SP, LOONGARCH_GPR_SP, stack_size);
emit_insn(ctx, jirl, LOONGARCH_GPR_ZERO, LOONGARCH_GPR_RA, 0);
} else {
/* trampoline called from function entry */
emit_insn(ctx, ldd, LOONGARCH_GPR_T0, LOONGARCH_GPR_SP, stack_size - 8);
emit_insn(ctx, ldd, LOONGARCH_GPR_FP, LOONGARCH_GPR_SP, stack_size - 16);
emit_insn(ctx, addid, LOONGARCH_GPR_SP, LOONGARCH_GPR_SP, stack_size);
emit_insn(ctx, ldd, LOONGARCH_GPR_RA, LOONGARCH_GPR_SP, 8);
emit_insn(ctx, ldd, LOONGARCH_GPR_FP, LOONGARCH_GPR_SP, 0);
emit_insn(ctx, addid, LOONGARCH_GPR_SP, LOONGARCH_GPR_SP, 16);
if (flags & BPF_TRAMP_F_SKIP_FRAME)
/* return to parent function */
emit_insn(ctx, jirl, LOONGARCH_GPR_ZERO, LOONGARCH_GPR_RA, 0);
else
/* return to traced function */
emit_insn(ctx, jirl, LOONGARCH_GPR_ZERO, LOONGARCH_GPR_T0, 0);
}
ret = ctx->idx;
out:
kfree(branches);
return ret;
}
int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *ro_image,
void *ro_image_end, const struct btf_func_model *m,
u32 flags, struct bpf_tramp_links *tlinks, void *func_addr)
{
int ret, size;
void *image, *tmp;
struct jit_ctx ctx;
size = ro_image_end - ro_image;
image = kvmalloc(size, GFP_KERNEL);
if (!image)
return -ENOMEM;
ctx.image = (union loongarch_instruction *)image;
ctx.ro_image = (union loongarch_instruction *)ro_image;
ctx.idx = 0;
jit_fill_hole(image, (unsigned int)(ro_image_end - ro_image));
ret = __arch_prepare_bpf_trampoline(&ctx, im, m, tlinks, func_addr, flags);
if (ret > 0 && validate_code(&ctx) < 0) {
ret = -EINVAL;
goto out;
}
tmp = bpf_arch_text_copy(ro_image, image, size);
if (IS_ERR(tmp)) {
ret = PTR_ERR(tmp);
goto out;
}
bpf_flush_icache(ro_image, ro_image_end);
out:
kvfree(image);
return ret < 0 ? ret : size;
}
int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags,
struct bpf_tramp_links *tlinks, void *func_addr)
{
int ret;
struct jit_ctx ctx;
struct bpf_tramp_image im;
ctx.image = NULL;
ctx.idx = 0;
ret = __arch_prepare_bpf_trampoline(&ctx, &im, m, tlinks, func_addr, flags);
/* Page align */
return ret < 0 ? ret : round_up(ret * LOONGARCH_INSN_SIZE, PAGE_SIZE);
}
struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
{
bool tmp_blinded = false, extra_pass = false;
@@ -1288,7 +1850,7 @@ skip_init_ctx:
build_epilogue(&ctx);
/* 3. Extra pass to validate JITed code */
if (validate_code(&ctx)) {
if (validate_ctx(&ctx)) {
bpf_jit_binary_free(header);
prog = orig_prog;
goto out_offset;
@@ -1342,7 +1904,6 @@ out:
if (tmp_blinded)
bpf_jit_prog_release_other(prog, prog == orig_prog ? tmp : orig_prog);
out_offset = -1;
return prog;
@@ -1354,6 +1915,16 @@ out_free:
goto out_offset;
}
bool bpf_jit_bypass_spec_v1(void)
{
return true;
}
bool bpf_jit_bypass_spec_v4(void)
{
return true;
}
/* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
bool bpf_jit_supports_subprog_tailcalls(void)
{

6
arch/loongarch/net/bpf_jit.h
View File

@@ -18,6 +18,7 @@ struct jit_ctx {
u32 *offset;
int num_exentries;
union loongarch_instruction *image;
union loongarch_instruction *ro_image;
u32 stack_size;
};
@@ -308,3 +309,8 @@ static inline int emit_tailcall_jmp(struct jit_ctx *ctx, u8 cond, enum loongarch
return -EINVAL;
}
static inline void bpf_flush_icache(void *start, void *end)
{
flush_icache_range((unsigned long)start, (unsigned long)end);
}

2
arch/loongarch/vdso/Makefile
View File

@@ -36,7 +36,7 @@ endif
# VDSO linker flags.
ldflags-y := -Bsymbolic --no-undefined -soname=linux-vdso.so.1 \
$(filter -E%,$(KBUILD_CFLAGS)) -nostdlib -shared --build-id -T
$(filter -E%,$(KBUILD_CFLAGS)) -shared --build-id -T
#
# Shared build commands.

2
arch/m68k/coldfire/gpio.c
View File

@@ -160,7 +160,7 @@ static struct gpio_chip mcfgpio_chip = {
.direction_input = mcfgpio_direction_input,
.direction_output = mcfgpio_direction_output,
.get = mcfgpio_get_value,
.set_rv = mcfgpio_set_value,
.set = mcfgpio_set_value,
.to_irq = mcfgpio_to_irq,
.base = 0,
.ngpio = MCFGPIO_PIN_MAX,

6
arch/mips/alchemy/common/gpiolib.c
View File

@@ -101,7 +101,7 @@ struct gpio_chip alchemy_gpio_chip[] = {
.direction_input = gpio1_direction_input,
.direction_output = gpio1_direction_output,
.get = gpio1_get,
.set_rv = gpio1_set,
.set = gpio1_set,
.to_irq = gpio1_to_irq,
.base = ALCHEMY_GPIO1_BASE,
.ngpio = ALCHEMY_GPIO1_NUM,
@@ -111,7 +111,7 @@ struct gpio_chip alchemy_gpio_chip[] = {
.direction_input = gpio2_direction_input,
.direction_output = gpio2_direction_output,
.get = gpio2_get,
.set_rv = gpio2_set,
.set = gpio2_set,
.to_irq = gpio2_to_irq,
.base = ALCHEMY_GPIO2_BASE,
.ngpio = ALCHEMY_GPIO2_NUM,
@@ -151,7 +151,7 @@ static struct gpio_chip au1300_gpiochip = {
.direction_input = alchemy_gpic_dir_input,
.direction_output = alchemy_gpic_dir_output,
.get = alchemy_gpic_get,
.set_rv = alchemy_gpic_set,
.set = alchemy_gpic_set,
.to_irq = alchemy_gpic_gpio_to_irq,
.base = AU1300_GPIO_BASE,
.ngpio = AU1300_GPIO_NUM,

2
arch/mips/bcm63xx/gpio.c
View File

@@ -131,7 +131,7 @@ static struct gpio_chip bcm63xx_gpio_chip = {
.direction_input = bcm63xx_gpio_direction_input,
.direction_output = bcm63xx_gpio_direction_output,
.get = bcm63xx_gpio_get,
.set_rv = bcm63xx_gpio_set,
.set = bcm63xx_gpio_set,
.base = 0,
};

2
arch/mips/kernel/gpio_txx9.c
View File

@@ -70,7 +70,7 @@ static int txx9_gpio_dir_out(struct gpio_chip *chip, unsigned int offset,
static struct gpio_chip txx9_gpio_chip = {
.get = txx9_gpio_get,
.set_rv = txx9_gpio_set,
.set = txx9_gpio_set,
.direction_input = txx9_gpio_dir_in,
.direction_output = txx9_gpio_dir_out,
.label = "TXx9",

2
arch/mips/kernel/setup.c
View File

@@ -458,7 +458,7 @@ static void __init mips_parse_crashkernel(void)
total_mem = memblock_phys_mem_size();
ret = parse_crashkernel(boot_command_line, total_mem,
&crash_size, &crash_base,
NULL, NULL);
NULL, NULL, NULL);
if (ret != 0 || crash_size <= 0)
return;

2
arch/mips/rb532/gpio.c
View File

@@ -164,7 +164,7 @@ static struct rb532_gpio_chip rb532_gpio_chip[] = {
.direction_input = rb532_gpio_direction_input,
.direction_output = rb532_gpio_direction_output,
.get = rb532_gpio_get,
.set_rv = rb532_gpio_set,
.set = rb532_gpio_set,
.to_irq = rb532_gpio_to_irq,
.base = 0,
.ngpio = 32,

2
arch/mips/txx9/generic/setup.c
View File

@@ -655,7 +655,7 @@ void __init txx9_iocled_init(unsigned long baseaddr,
if (!iocled->mmioaddr)
goto out_free;
iocled->chip.get = txx9_iocled_get;
iocled->chip.set_rv = txx9_iocled_set;
iocled->chip.set = txx9_iocled_set;
iocled->chip.direction_input = txx9_iocled_dir_in;
iocled->chip.direction_output = txx9_iocled_dir_out;
iocled->chip.label = "iocled";

2
arch/openrisc/include/asm/mmu.h
View File

@@ -15,7 +15,7 @@
#ifndef __ASM_OPENRISC_MMU_H
#define __ASM_OPENRISC_MMU_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef unsigned long mm_context_t;
#endif

8
arch/openrisc/include/asm/page.h
View File

@@ -25,7 +25,7 @@
*/
#include <asm/setup.h>
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#define clear_page(page) memset((page), 0, PAGE_SIZE)
#define copy_page(to, from) memcpy((to), (from), PAGE_SIZE)
@@ -55,10 +55,10 @@ typedef struct page *pgtable_t;
#define __pgd(x) ((pgd_t) { (x) })
#define __pgprot(x) ((pgprot_t) { (x) })
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
@@ -73,7 +73,7 @@ static inline unsigned long virt_to_pfn(const void *kaddr)
#define virt_addr_valid(kaddr) (pfn_valid(virt_to_pfn(kaddr)))
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#include <asm-generic/memory_model.h>
#include <asm-generic/getorder.h>

4
arch/openrisc/include/asm/pgtable.h
View File

@@ -23,7 +23,7 @@
#include <asm-generic/pgtable-nopmd.h>
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <asm/mmu.h>
#include <asm/fixmap.h>
@@ -430,5 +430,5 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
typedef pte_t *pte_addr_t;
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* __ASM_OPENRISC_PGTABLE_H */

4
arch/openrisc/include/asm/processor.h
View File

@@ -39,7 +39,7 @@
*/
#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
struct task_struct;
@@ -78,5 +78,5 @@ void show_registers(struct pt_regs *regs);
#define cpu_relax() barrier()
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* __ASM_OPENRISC_PROCESSOR_H */

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