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@@ -122,7 +122,9 @@ static const struct {
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};
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static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
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static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq);
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static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba,
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unsigned long freq, char *name);
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static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq);
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static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
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{
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@@ -506,10 +508,9 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
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if (ret)
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return ret;
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if (phy->power_count) {
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if (phy->power_count)
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phy_power_off(phy);
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phy_exit(phy);
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}
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/* phy initialization - calibrate the phy */
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ret = phy_init(phy);
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@@ -597,13 +598,14 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
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*
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* @hba: host controller instance
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* @is_pre_scale_up: flag to check if pre scale up condition.
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* @freq: target opp freq
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* Return: zero for success and non-zero in case of a failure.
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*/
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static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up)
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static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsigned long freq)
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{
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struct ufs_qcom_host *host = ufshcd_get_variant(hba);
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struct ufs_clk_info *clki;
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unsigned long core_clk_rate = 0;
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unsigned long clk_freq = 0;
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u32 core_clk_cycles_per_us;
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/*
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@@ -615,22 +617,34 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up)
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if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba))
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return 0;
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if (hba->use_pm_opp && freq != ULONG_MAX) {
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clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk");
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if (clk_freq)
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goto cfg_timers;
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}
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list_for_each_entry(clki, &hba->clk_list_head, list) {
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if (!strcmp(clki->name, "core_clk")) {
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if (freq == ULONG_MAX) {
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clk_freq = clki->max_freq;
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break;
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}
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if (is_pre_scale_up)
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core_clk_rate = clki->max_freq;
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clk_freq = clki->max_freq;
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else
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core_clk_rate = clk_get_rate(clki->clk);
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clk_freq = clk_get_rate(clki->clk);
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break;
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}
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}
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cfg_timers:
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/* If frequency is smaller than 1MHz, set to 1MHz */
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if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
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core_clk_rate = DEFAULT_CLK_RATE_HZ;
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if (clk_freq < DEFAULT_CLK_RATE_HZ)
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clk_freq = DEFAULT_CLK_RATE_HZ;
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core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
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core_clk_cycles_per_us = clk_freq / USEC_PER_SEC;
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if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
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ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
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/*
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@@ -650,13 +664,13 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
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switch (status) {
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case PRE_CHANGE:
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if (ufs_qcom_cfg_timers(hba, false)) {
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if (ufs_qcom_cfg_timers(hba, false, ULONG_MAX)) {
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dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
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__func__);
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return -EINVAL;
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}
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err = ufs_qcom_set_core_clk_ctrl(hba, ULONG_MAX);
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err = ufs_qcom_set_core_clk_ctrl(hba, true, ULONG_MAX);
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if (err)
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dev_err(hba->dev, "cfg core clk ctrl failed\n");
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/*
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@@ -928,17 +942,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
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break;
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case POST_CHANGE:
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if (ufs_qcom_cfg_timers(hba, false)) {
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dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
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__func__);
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/*
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* we return error code at the end of the routine,
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* but continue to configure UFS_PHY_TX_LANE_ENABLE
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* and bus voting as usual
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*/
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ret = -EINVAL;
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}
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/* cache the power mode parameters to use internally */
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memcpy(&host->dev_req_params,
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dev_req_params, sizeof(*dev_req_params));
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@@ -1414,29 +1417,46 @@ static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
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return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
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}
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static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq)
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static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq)
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{
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struct ufs_qcom_host *host = ufshcd_get_variant(hba);
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struct list_head *head = &hba->clk_list_head;
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struct ufs_clk_info *clki;
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u32 cycles_in_1us = 0;
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u32 core_clk_ctrl_reg;
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unsigned long clk_freq;
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int err;
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if (hba->use_pm_opp && freq != ULONG_MAX) {
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clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro");
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if (clk_freq) {
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cycles_in_1us = ceil(clk_freq, HZ_PER_MHZ);
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goto set_core_clk_ctrl;
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}
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}
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list_for_each_entry(clki, head, list) {
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if (!IS_ERR_OR_NULL(clki->clk) &&
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!strcmp(clki->name, "core_clk_unipro")) {
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if (!clki->max_freq)
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if (!clki->max_freq) {
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cycles_in_1us = 150; /* default for backwards compatibility */
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else if (freq == ULONG_MAX)
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break;
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}
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if (freq == ULONG_MAX) {
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cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ);
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break;
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}
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if (is_scale_up)
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cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ);
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else
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cycles_in_1us = ceil(freq, HZ_PER_MHZ);
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cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ);
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break;
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}
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}
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set_core_clk_ctrl:
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err = ufshcd_dme_get(hba,
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UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
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&core_clk_ctrl_reg);
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@@ -1473,13 +1493,13 @@ static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long f
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{
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int ret;
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ret = ufs_qcom_cfg_timers(hba, true);
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ret = ufs_qcom_cfg_timers(hba, true, freq);
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if (ret) {
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dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__);
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return ret;
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}
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/* set unipro core clock attributes and clear clock divider */
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return ufs_qcom_set_core_clk_ctrl(hba, freq);
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return ufs_qcom_set_core_clk_ctrl(hba, true, freq);
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}
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static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
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@@ -1510,8 +1530,15 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
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static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq)
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{
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int ret;
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ret = ufs_qcom_cfg_timers(hba, false, freq);
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if (ret) {
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dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__);
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return ret;
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}
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/* set unipro core clock attributes and clear clock divider */
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return ufs_qcom_set_core_clk_ctrl(hba, freq);
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return ufs_qcom_set_core_clk_ctrl(hba, false, freq);
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}
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static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
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@@ -2092,11 +2119,53 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba)
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return 0;
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}
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static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba,
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unsigned long freq, char *name)
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{
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struct ufs_clk_info *clki;
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struct dev_pm_opp *opp;
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unsigned long clk_freq;
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int idx = 0;
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bool found = false;
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opp = dev_pm_opp_find_freq_exact_indexed(hba->dev, freq, 0, true);
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if (IS_ERR(opp)) {
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dev_err(hba->dev, "Failed to find OPP for exact frequency %lu\n", freq);
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return 0;
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}
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list_for_each_entry(clki, &hba->clk_list_head, list) {
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if (!strcmp(clki->name, name)) {
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found = true;
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break;
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}
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idx++;
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}
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if (!found) {
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dev_err(hba->dev, "Failed to find clock '%s' in clk list\n", name);
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dev_pm_opp_put(opp);
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return 0;
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}
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clk_freq = dev_pm_opp_get_freq_indexed(opp, idx);
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dev_pm_opp_put(opp);
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return clk_freq;
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}
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static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq)
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{
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u32 gear = 0;
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u32 gear = UFS_HS_DONT_CHANGE;
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unsigned long unipro_freq;
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switch (freq) {
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if (!hba->use_pm_opp)
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return gear;
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unipro_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro");
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switch (unipro_freq) {
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case 403000000:
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gear = UFS_HS_G5;
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break;
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@@ -2116,10 +2185,10 @@ static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq)
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break;
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default:
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dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq);
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break;
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return UFS_HS_DONT_CHANGE;
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}
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return gear;
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return min_t(u32, gear, hba->max_pwr_info.info.gear_rx);
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}
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/*
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