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drm/amdgpu: access ltr through pci cfg space

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Access ltr through pci cfg space instead of mmio while programing
aspm on gfx12

Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Frank Min
2024-06-19 15:54:38 +08:00
committed by Alex Deucher
parent 6bab222b8b
commit 748bd8ebae
1 changed files with 10 additions and 4 deletions
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14
drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
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@@ -345,6 +345,7 @@ static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev)
{
#ifdef CONFIG_PCIEASPM
uint32_t def, data;
u16 devctl2, ltr;
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);
data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
@@ -374,12 +375,17 @@ static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev)
if (def != data)
WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2);
data = def = devctl2;
data &= ~PCI_EXP_DEVCTL2_LTR_EN;
if (def != data)
WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, (u16)data);
WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
ltr = pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_LTR);
if (ltr) {
pci_write_config_dword(adev->pdev, ltr + PCI_LTR_MAX_SNOOP_LAT, 0x10011001);
}
#if 0
/* regPSWUSP0_PCIE_LC_CNTL2 should be replace by PCIE_LC_CNTL2 or someone else ? */