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media: staging/ipu7: avoid division by 64-bit value

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On 32-bit targets, this causes a link failure:

x86_64-linux-ld: drivers/staging/media/ipu7/ipu7-isys-csi-phy.o: in function `ipu7_isys_phy_config':
ipu7-isys-csi-phy.c:(.text+0x1509): undefined reference to `__udivdi3'

Note that this does not divide a 64-bit number by a 32-bit one as usual,
but the other way round, which is something that the compiler should
really be able to figure out but does not (as of gcc-15).

A few lines higher, a similar division is done using the incorrect div_u64()
that truncates the 64-bit divisor to 32 bits.

Change both to use the safe but slow div64_u64() helper.

Fixes: a516d36bdc ("media: staging/ipu7: add IPU7 input system device driver")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
Arnd Bergmann
2025-07-09 16:56:56 +02:00
committed by Hans Verkuil
parent 2946bac895
commit 6af7e00a92
1 changed files with 4 additions and 4 deletions
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8
drivers/staging/media/ipu7/ipu7-isys-csi-phy.c
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@@ -734,6 +734,7 @@ static void ipu7_isys_cphy_config(struct ipu7_isys *isys, u8 id, u8 lanes,
u16 reg;
u16 val;
u32 i;
u64 r64;
u32 r;
if (is_ipu7p5(isys->adev->isp->hw_ver))
@@ -806,8 +807,8 @@ static void ipu7_isys_cphy_config(struct ipu7_isys *isys, u8 id, u8 lanes,
dwc_phy_write_mask(isys, id, reg, 2, 0, 2);
}
deass_thresh = (u16)div_u64_rem(7 * 1000 * 6, mbps * 5U, &r) + 1;
if (r != 0)
deass_thresh = (u16)div64_u64_rem(7 * 1000 * 6, mbps * 5U, &r64) + 1;
if (r64 != 0)
deass_thresh++;
reg = CORE_DIG_RW_TRIO0_2;
@@ -815,8 +816,7 @@ static void ipu7_isys_cphy_config(struct ipu7_isys *isys, u8 id, u8 lanes,
dwc_phy_write_mask(isys, id, reg + 0x400 * i,
deass_thresh, 0, 7);
delay_thresh =
((224U - (9U * 7U)) * 1000U) / (5U * mbps) - 7U;
delay_thresh = div64_u64((224U - (9U * 7U)) * 1000U, 5U * mbps) - 7u;
if (delay_thresh < 1)
delay_thresh = 1;