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drm/i915: add .fence_priority_display to parent interface
Add .fence_priority_display() to display parent interface, removing a display dependency on gem/i915_gem_object.h. This allows us to remove the xe compat gem/i915_gem_object.h. v2: Don't mix this with the rps interface (Ville) v3: Rebase Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/c7782862956e3aa59eaeb6dcf80906c1fc063ae1.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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@@ -64,3 +64,9 @@ bool intel_parent_has_fenced_regions(struct intel_display *display)
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{
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return display->parent->has_fenced_regions && display->parent->has_fenced_regions(display->drm);
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}
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void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence)
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{
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if (display->parent->fence_priority_display)
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display->parent->fence_priority_display(fence);
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}
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@@ -21,4 +21,6 @@ bool intel_parent_vgpu_active(struct intel_display *display);
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bool intel_parent_has_fenced_regions(struct intel_display *display);
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void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence);
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#endif /* __INTEL_PARENT_H__ */
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@@ -45,7 +45,6 @@
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#include <drm/drm_panic.h>
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#include <drm/drm_print.h>
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#include "gem/i915_gem_object.h"
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#include "i9xx_plane_regs.h"
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#include "intel_cdclk.h"
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#include "intel_cursor.h"
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@@ -56,6 +55,7 @@
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#include "intel_fb_pin.h"
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#include "intel_fbdev.h"
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#include "intel_panic.h"
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#include "intel_parent.h"
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#include "intel_plane.h"
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#include "intel_psr.h"
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#include "skl_scaler.h"
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@@ -1180,8 +1180,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
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goto unpin_fb;
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if (new_plane_state->uapi.fence) {
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i915_gem_fence_wait_priority_display(new_plane_state->uapi.fence);
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intel_parent_fence_priority_display(display, new_plane_state->uapi.fence);
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intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
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new_plane_state->uapi.fence);
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}
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@@ -750,12 +750,19 @@ static bool has_fenced_regions(struct drm_device *drm)
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return intel_gt_support_legacy_fencing(to_gt(to_i915(drm)));
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}
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static void fence_priority_display(struct dma_fence *fence)
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{
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if (dma_fence_is_i915(fence))
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i915_gem_fence_wait_priority_display(fence);
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}
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static const struct intel_display_parent_interface parent = {
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.rpm = &i915_display_rpm_interface,
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.irq = &i915_display_irq_interface,
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.rps = &i915_display_rps_interface,
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.vgpu_active = vgpu_active,
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.has_fenced_regions = has_fenced_regions,
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.fence_priority_display = fence_priority_display,
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};
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const struct intel_display_parent_interface *i915_driver_parent_interface(void)
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@@ -1,13 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/* Copyright © 2025 Intel Corporation */
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#ifndef __I915_GEM_OBJECT_H__
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#define __I915_GEM_OBJECT_H__
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struct dma_fence;
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static inline void i915_gem_fence_wait_priority_display(struct dma_fence *fence)
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{
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}
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#endif
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@@ -64,6 +64,9 @@ struct intel_display_parent_interface {
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/** @has_fenced_regions: Support legacy fencing? Optional. */
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bool (*has_fenced_regions)(struct drm_device *drm);
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/** @fence_priority_display: Set display priority. Optional. */
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void (*fence_priority_display)(struct dma_fence *fence);
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};
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#endif
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