drm/i915: add .fence_priority_display to parent interface

Add .fence_priority_display() to display parent interface, removing a
display dependency on gem/i915_gem_object.h.

This allows us to remove the xe compat gem/i915_gem_object.h.

v2: Don't mix this with the rps interface (Ville)

v3: Rebase

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/c7782862956e3aa59eaeb6dcf80906c1fc063ae1.1763370931.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2025-11-17 11:16:16 +02:00
parent 69c9b1861e
commit 55fc11ce96
6 changed files with 20 additions and 16 deletions

View File

@@ -64,3 +64,9 @@ bool intel_parent_has_fenced_regions(struct intel_display *display)
{
return display->parent->has_fenced_regions && display->parent->has_fenced_regions(display->drm);
}
void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence)
{
if (display->parent->fence_priority_display)
display->parent->fence_priority_display(fence);
}

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@@ -21,4 +21,6 @@ bool intel_parent_vgpu_active(struct intel_display *display);
bool intel_parent_has_fenced_regions(struct intel_display *display);
void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence);
#endif /* __INTEL_PARENT_H__ */

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@@ -45,7 +45,6 @@
#include <drm/drm_panic.h>
#include <drm/drm_print.h>
#include "gem/i915_gem_object.h"
#include "i9xx_plane_regs.h"
#include "intel_cdclk.h"
#include "intel_cursor.h"
@@ -56,6 +55,7 @@
#include "intel_fb_pin.h"
#include "intel_fbdev.h"
#include "intel_panic.h"
#include "intel_parent.h"
#include "intel_plane.h"
#include "intel_psr.h"
#include "skl_scaler.h"
@@ -1180,8 +1180,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
goto unpin_fb;
if (new_plane_state->uapi.fence) {
i915_gem_fence_wait_priority_display(new_plane_state->uapi.fence);
intel_parent_fence_priority_display(display, new_plane_state->uapi.fence);
intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
new_plane_state->uapi.fence);
}

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@@ -750,12 +750,19 @@ static bool has_fenced_regions(struct drm_device *drm)
return intel_gt_support_legacy_fencing(to_gt(to_i915(drm)));
}
static void fence_priority_display(struct dma_fence *fence)
{
if (dma_fence_is_i915(fence))
i915_gem_fence_wait_priority_display(fence);
}
static const struct intel_display_parent_interface parent = {
.rpm = &i915_display_rpm_interface,
.irq = &i915_display_irq_interface,
.rps = &i915_display_rps_interface,
.vgpu_active = vgpu_active,
.has_fenced_regions = has_fenced_regions,
.fence_priority_display = fence_priority_display,
};
const struct intel_display_parent_interface *i915_driver_parent_interface(void)

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@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2025 Intel Corporation */
#ifndef __I915_GEM_OBJECT_H__
#define __I915_GEM_OBJECT_H__
struct dma_fence;
static inline void i915_gem_fence_wait_priority_display(struct dma_fence *fence)
{
}
#endif

View File

@@ -64,6 +64,9 @@ struct intel_display_parent_interface {
/** @has_fenced_regions: Support legacy fencing? Optional. */
bool (*has_fenced_regions)(struct drm_device *drm);
/** @fence_priority_display: Set display priority. Optional. */
void (*fence_priority_display)(struct dma_fence *fence);
};
#endif