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arm64/sysreg: Add BRBE registers and fields
This patch adds definitions related to the Branch Record Buffer Extension (BRBE) as per ARM DDI 0487K.a. These will be used by KVM and a BRBE driver in subsequent patches. Some existing BRBE definitions in asm/sysreg.h are replaced with equivalent generated definitions. Cc: Marc Zyngier <maz@kernel.org> Reviewed-by: Mark Brown <broonie@kernel.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Tested-by: James Clark <james.clark@linaro.org> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> tested-by: Adam Young <admiyo@os.amperecomputing.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20250611-arm-brbe-v19-v23-1-e7775563036e@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Anshuman Khandual
committed by
Will Deacon
Will Deacon
parent
860a831de1
commit
52e4a56ab8
@@ -202,16 +202,8 @@
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#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
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#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
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#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
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#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
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#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
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#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
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#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
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#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
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#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
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#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
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#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
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#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
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#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
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@@ -277,8 +269,6 @@
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/* ETM */
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#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
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#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
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#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
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#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
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#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
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@@ -821,6 +811,12 @@
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#define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
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#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
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/*
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* BRBE Instructions
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*/
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#define BRB_IALL_INSN __emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f))
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#define BRB_INJ_INSN __emit_inst(0xd5000000 | OP_BRB_INJ | (0x1f))
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/* Common SCTLR_ELx flags. */
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#define SCTLR_ELx_ENTP2 (BIT(60))
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#define SCTLR_ELx_DSSBS (BIT(44))
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@@ -1329,6 +1329,138 @@ UnsignedEnum 3:0 MTEPERM
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EndEnum
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EndSysreg
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SysregFields BRBINFx_EL1
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Res0 63:47
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Field 46 CCU
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Field 45:40 CC_EXP
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Field 39:32 CC_MANT
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Res0 31:18
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Field 17 LASTFAILED
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Field 16 T
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Res0 15:14
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Enum 13:8 TYPE
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0b000000 DIRECT_UNCOND
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0b000001 INDIRECT
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0b000010 DIRECT_LINK
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0b000011 INDIRECT_LINK
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0b000101 RET
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0b000111 ERET
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0b001000 DIRECT_COND
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0b100001 DEBUG_HALT
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0b100010 CALL
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0b100011 TRAP
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0b100100 SERROR
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0b100110 INSN_DEBUG
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0b100111 DATA_DEBUG
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0b101010 ALIGN_FAULT
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0b101011 INSN_FAULT
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0b101100 DATA_FAULT
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0b101110 IRQ
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0b101111 FIQ
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0b110000 IMPDEF_TRAP_EL3
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0b111001 DEBUG_EXIT
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EndEnum
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Enum 7:6 EL
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0b00 EL0
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0b01 EL1
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0b10 EL2
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0b11 EL3
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EndEnum
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Field 5 MPRED
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Res0 4:2
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Enum 1:0 VALID
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0b00 NONE
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0b01 TARGET
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0b10 SOURCE
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0b11 FULL
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EndEnum
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EndSysregFields
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SysregFields BRBCR_ELx
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Res0 63:24
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Field 23 EXCEPTION
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Field 22 ERTN
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Res0 21:10
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Field 9 FZPSS
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Field 8 FZP
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Res0 7
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Enum 6:5 TS
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0b01 VIRTUAL
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0b10 GUEST_PHYSICAL
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0b11 PHYSICAL
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EndEnum
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Field 4 MPRED
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Field 3 CC
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Res0 2
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Field 1 ExBRE
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Field 0 E0BRE
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EndSysregFields
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Sysreg BRBCR_EL1 2 1 9 0 0
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Fields BRBCR_ELx
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EndSysreg
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Sysreg BRBFCR_EL1 2 1 9 0 1
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Res0 63:30
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Enum 29:28 BANK
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0b00 BANK_0
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0b01 BANK_1
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EndEnum
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Res0 27:23
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Field 22 CONDDIR
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Field 21 DIRCALL
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Field 20 INDCALL
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Field 19 RTN
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Field 18 INDIRECT
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Field 17 DIRECT
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Field 16 EnI
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Res0 15:8
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Field 7 PAUSED
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Field 6 LASTFAILED
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Res0 5:0
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EndSysreg
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Sysreg BRBTS_EL1 2 1 9 0 2
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Field 63:0 TS
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EndSysreg
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Sysreg BRBINFINJ_EL1 2 1 9 1 0
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Fields BRBINFx_EL1
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EndSysreg
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Sysreg BRBSRCINJ_EL1 2 1 9 1 1
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Field 63:0 ADDRESS
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EndSysreg
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Sysreg BRBTGTINJ_EL1 2 1 9 1 2
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Field 63:0 ADDRESS
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EndSysreg
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Sysreg BRBIDR0_EL1 2 1 9 2 0
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Res0 63:16
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Enum 15:12 CC
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0b0101 20_BIT
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EndEnum
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Enum 11:8 FORMAT
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0b0000 FORMAT_0
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EndEnum
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Enum 7:0 NUMREC
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0b00001000 8
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0b00010000 16
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0b00100000 32
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0b01000000 64
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EndEnum
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EndSysreg
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Sysreg BRBCR_EL2 2 4 9 0 0
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Fields BRBCR_ELx
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EndSysreg
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Sysreg BRBCR_EL12 2 5 9 0 0
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Fields BRBCR_ELx
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EndSysreg
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Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4
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Res0 63:60
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UnsignedEnum 59:56 F64MM
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