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drm/amdgpu: Enable RAS for vcn 5.0.1
Enable vcn ras posion processing and aca error logging Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mangesh Gadre
committed by
Alex Deucher
Alex Deucher
parent
076873e5b3
commit
5035caf18d
@@ -46,7 +46,7 @@ static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev);
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static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst,
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enum amd_powergating_state state);
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static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring);
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static void vcn_v5_0_1_set_ras_funcs(struct amdgpu_device *adev);
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/**
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* vcn_v5_0_1_early_init - set function pointers and load microcode
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*
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@@ -66,6 +66,7 @@ static int vcn_v5_0_1_early_init(struct amdgpu_ip_block *ip_block)
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vcn_v5_0_1_set_unified_ring_funcs(adev);
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vcn_v5_0_1_set_irq_funcs(adev);
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vcn_v5_0_1_set_ras_funcs(adev);
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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adev->vcn.inst[i].set_pg_state = vcn_v5_0_1_set_pg_state;
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@@ -113,6 +114,10 @@ static int vcn_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block)
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if (r)
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return r;
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/* VCN POISON TRAP */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
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VCN_5_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq);
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for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
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vcn_inst = GET_INST(VCN, i);
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@@ -279,6 +284,9 @@ static int vcn_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block)
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vinst->set_pg_state(vinst, AMD_PG_STATE_GATE);
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}
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
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amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0);
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return 0;
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}
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@@ -1391,10 +1399,24 @@ static int vcn_v5_0_1_process_interrupt(struct amdgpu_device *adev, struct amdgp
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return 0;
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}
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static int vcn_v5_0_1_set_ras_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned int type,
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enum amdgpu_interrupt_state state)
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{
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return 0;
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}
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static const struct amdgpu_irq_src_funcs vcn_v5_0_1_irq_funcs = {
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.process = vcn_v5_0_1_process_interrupt,
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};
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static const struct amdgpu_irq_src_funcs vcn_v5_0_1_ras_irq_funcs = {
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.set = vcn_v5_0_1_set_ras_interrupt_state,
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.process = amdgpu_vcn_process_poison_irq,
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};
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/**
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* vcn_v5_0_1_set_irq_funcs - set VCN block interrupt irq functions
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*
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@@ -1408,7 +1430,12 @@ static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev)
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
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adev->vcn.inst->irq.num_types++;
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adev->vcn.inst->irq.funcs = &vcn_v5_0_1_irq_funcs;
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adev->vcn.inst->ras_poison_irq.num_types = 1;
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adev->vcn.inst->ras_poison_irq.funcs = &vcn_v5_0_1_ras_irq_funcs;
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}
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static const struct amd_ip_funcs vcn_v5_0_1_ip_funcs = {
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@@ -1440,3 +1467,139 @@ const struct amdgpu_ip_block_version vcn_v5_0_1_ip_block = {
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.rev = 1,
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.funcs = &vcn_v5_0_1_ip_funcs,
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};
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static uint32_t vcn_v5_0_1_query_poison_by_instance(struct amdgpu_device *adev,
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uint32_t instance, uint32_t sub_block)
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{
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uint32_t poison_stat = 0, reg_value = 0;
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switch (sub_block) {
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case AMDGPU_VCN_V5_0_1_VCPU_VCODEC:
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reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);
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poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
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break;
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default:
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break;
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}
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if (poison_stat)
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dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
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instance, sub_block);
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return poison_stat;
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}
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static bool vcn_v5_0_1_query_poison_status(struct amdgpu_device *adev)
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{
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uint32_t inst, sub;
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uint32_t poison_stat = 0;
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for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
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for (sub = 0; sub < AMDGPU_VCN_V5_0_1_MAX_SUB_BLOCK; sub++)
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poison_stat +=
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vcn_v5_0_1_query_poison_by_instance(adev, inst, sub);
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return !!poison_stat;
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}
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static const struct amdgpu_ras_block_hw_ops vcn_v5_0_1_ras_hw_ops = {
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.query_poison_status = vcn_v5_0_1_query_poison_status,
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};
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static int vcn_v5_0_1_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,
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enum aca_smu_type type, void *data)
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{
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struct aca_bank_info info;
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u64 misc0;
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int ret;
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ret = aca_bank_info_decode(bank, &info);
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if (ret)
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return ret;
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misc0 = bank->regs[ACA_REG_IDX_MISC0];
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switch (type) {
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case ACA_SMU_TYPE_UE:
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bank->aca_err_type = ACA_ERROR_TYPE_UE;
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ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE,
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1ULL);
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break;
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case ACA_SMU_TYPE_CE:
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bank->aca_err_type = ACA_ERROR_TYPE_CE;
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ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,
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ACA_REG__MISC0__ERRCNT(misc0));
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break;
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default:
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return -EINVAL;
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}
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return ret;
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}
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/* reference to smu driver if header file */
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static int vcn_v5_0_1_err_codes[] = {
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14, 15, /* VCN */
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};
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static bool vcn_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
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enum aca_smu_type type, void *data)
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{
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u32 instlo;
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instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
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instlo &= GENMASK(31, 1);
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if (instlo != mmSMNAID_AID0_MCA_SMU)
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return false;
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if (aca_bank_check_error_codes(handle->adev, bank,
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vcn_v5_0_1_err_codes,
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ARRAY_SIZE(vcn_v5_0_1_err_codes)))
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return false;
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return true;
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}
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static const struct aca_bank_ops vcn_v5_0_1_aca_bank_ops = {
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.aca_bank_parser = vcn_v5_0_1_aca_bank_parser,
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.aca_bank_is_valid = vcn_v5_0_1_aca_bank_is_valid,
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};
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static const struct aca_info vcn_v5_0_1_aca_info = {
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.hwip = ACA_HWIP_TYPE_SMU,
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.mask = ACA_ERROR_UE_MASK,
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.bank_ops = &vcn_v5_0_1_aca_bank_ops,
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};
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static int vcn_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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int r;
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r = amdgpu_ras_block_late_init(adev, ras_block);
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if (r)
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return r;
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r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN,
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&vcn_v5_0_1_aca_info, NULL);
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if (r)
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goto late_fini;
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return 0;
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late_fini:
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amdgpu_ras_block_late_fini(adev, ras_block);
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return r;
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}
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static struct amdgpu_vcn_ras vcn_v5_0_1_ras = {
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.ras_block = {
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.hw_ops = &vcn_v5_0_1_ras_hw_ops,
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.ras_late_init = vcn_v5_0_1_ras_late_init,
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},
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};
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static void vcn_v5_0_1_set_ras_funcs(struct amdgpu_device *adev)
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{
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adev->vcn.ras = &vcn_v5_0_1_ras;
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}
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@@ -27,6 +27,13 @@
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#define regVCN_RRMT_CNTL 0x0940
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#define regVCN_RRMT_CNTL_BASE_IDX 1
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enum amdgpu_vcn_v5_0_1_sub_block {
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AMDGPU_VCN_V5_0_1_VCPU_VCODEC = 0,
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AMDGPU_VCN_V5_0_1_MAX_SUB_BLOCK,
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};
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extern const struct amdgpu_ip_block_version vcn_v5_0_1_ip_block;
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#endif /* __VCN_v5_0_1_H__ */
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