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drm/i915/vrr: Write DC balance params to hw registers

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Write DC Balance parameters to hw registers.

--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)

--v3:
- Write registers at compute config.
- Update condition for write.

--v4:
- Address issue with state checker.

--v5:
- Initialise some more dc balance register while enabling VRR.

--v6:
- FLIPLINE_CFG need to be configure at last, as it is double buffer
arming point.

--v7:
- Initialise and reset live value of vmax and vmin as well.

--v8:
- Add separate functions while writing hw registers. (Ankit)

--v9:
- Add DC Balance counter enable bit to this patch. (Ankit)

--v10:
- Add rigister writes to vrr_enable/disable. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-12-mitulkumar.ajitkumar.golani@intel.com
This commit is contained in:
Mitul Golani
2025-12-23 16:15:33 +05:30
committed by Ankit Nautiyal
parent d780bbebaa
commit 4ca36702d8
1 changed files with 76 additions and 0 deletions
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76
drivers/gpu/drm/i915/display/intel_vrr.c
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@@ -781,6 +781,80 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
intel_vrr_hw_flipline(crtc_state) - 1);
}
static void
intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
if (!crtc_state->vrr.dc_balance.enable)
return;
intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder),
VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder),
VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder),
VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),
VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
crtc_state->vrr.dc_balance.vmin - 1);
intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
crtc_state->vrr.dc_balance.vmax - 1);
intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
crtc_state->vrr.dc_balance.max_increase);
intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
crtc_state->vrr.dc_balance.max_decrease);
intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
crtc_state->vrr.dc_balance.guardband);
intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
crtc_state->vrr.dc_balance.slope);
intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
crtc_state->vrr.dc_balance.vblank_target);
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
ADAPTIVE_SYNC_COUNTER_EN);
}
static void
intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
{
struct intel_display *display = to_intel_display(old_crtc_state);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
if (!old_crtc_state->vrr.dc_balance.enable)
return;
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0);
intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0);
intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0);
intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0);
intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
}
static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
bool cmrr_enable)
{
@@ -827,6 +901,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
return;
intel_vrr_set_vrr_timings(crtc_state);
intel_vrr_enable_dc_balancing(crtc_state);
if (!intel_vrr_always_use_vrr_tg(display))
intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
@@ -842,6 +917,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
if (!intel_vrr_always_use_vrr_tg(display))
intel_vrr_tg_disable(old_crtc_state);
intel_vrr_disable_dc_balancing(old_crtc_state);
intel_vrr_set_fixed_rr_timings(old_crtc_state);
}