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Merge tag 'x86_misc_for_v6.4_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Browse Source 
Pull misc x86 updates from Borislav Petkov:

 - Add a x86 hw vulnerabilities section to MAINTAINERS so that the folks
   involved in it can get CCed on patches

 - Add some more CPUID leafs to the kcpuid tool and extend its
   functionality to be more useful when grepping for CPUID bits

* tag 'x86_misc_for_v6.4_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  MAINTAINERS: Add x86 hardware vulnerabilities section
  tools/x86/kcpuid: Dump the CPUID function in detailed view
  tools/x86/kcpuid: Update AMD leaf Fn80000001
  tools/x86/kcpuid: Fix avx512bw and avx512lvl fields in Fn00000007
This commit is contained in:
Linus Torvalds
2023-04-25 10:27:02 -07:00
parent e3420f98f8 5910f06503
commit 4a4a28fca6
3 changed files with 94 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
MAINTAINERS
View File

@@ -22663,6 +22663,17 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/asm
F: arch/x86/entry/
X86 HARDWARE VULNERABILITIES
M: Thomas Gleixner <tglx@linutronix.de>
M: Borislav Petkov <bp@alien8.de>
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
R: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
S: Maintained
F: Documentation/admin-guide/hw-vuln/
F: arch/x86/include/asm/nospec-branch.h
F: arch/x86/kernel/cpu/bugs.c
X86 MCE INFRASTRUCTURE
M: Tony Luck <tony.luck@intel.com>
M: Borislav Petkov <bp@alien8.de>

65
tools/arch/x86/kcpuid/cpuid.csv
View File

@@ -184,8 +184,8 @@
7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr
7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr
7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr
7, 0, EBX, 26, avx512bw, AVX512 Byte & Word instr
7, 0, EBX, 28, avx512vl, AVX512 Vector Length Extentions (VL)
7, 0, EBX, 30, avx512bw, AVX512 Byte & Word instr
7, 0, EBX, 31, avx512vl, AVX512 Vector Length Extentions (VL)
7, 0, ECX, 0, prefetchwt1, X
7, 0, ECX, 1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions
7, 0, ECX, 2, umip, User-mode Instruction Prevention
@@ -340,19 +340,70 @@
# According to SDM
# 40000000H - 4FFFFFFFH is invalid range
# Leaf 80000001H
# Extended Processor Signature and Feature Bits
0x80000001, 0, ECX, 0, lahf_lm, LAHF/SAHF available in 64-bit mode
0x80000001, 0, ECX, 5, lzcnt, LZCNT
0x80000001, 0, ECX, 8, prefetchw, PREFETCHW
0x80000001, 0, EAX, 27:20, extfamily, Extended family
0x80000001, 0, EAX, 19:16, extmodel, Extended model
0x80000001, 0, EAX, 11:8, basefamily, Description of Family
0x80000001, 0, EAX, 11:8, basemodel, Model numbers vary with product
0x80000001, 0, EAX, 3:0, stepping, Processor stepping (revision) for a specific model
0x80000001, 0, EBX, 31:28, pkgtype, Specifies the package type
0x80000001, 0, ECX, 0, lahf_lm, LAHF/SAHF available in 64-bit mode
0x80000001, 0, ECX, 1, cmplegacy, Core multi-processing legacy mode
0x80000001, 0, ECX, 2, svm, Indicates support for: VMRUN, VMLOAD, VMSAVE, CLGI, VMMCALL, and INVLPGA
0x80000001, 0, ECX, 3, extapicspace, Extended APIC register space
0x80000001, 0, ECX, 4, altmovecr8, Indicates support for LOCK MOV CR0 means MOV CR8
0x80000001, 0, ECX, 5, lzcnt, LZCNT
0x80000001, 0, ECX, 6, sse4a, EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support
0x80000001, 0, ECX, 7, misalignsse, Misaligned SSE Mode
0x80000001, 0, ECX, 8, prefetchw, PREFETCHW
0x80000001, 0, ECX, 9, osvw, OS Visible Work-around support
0x80000001, 0, ECX, 10, ibs, Instruction Based Sampling
0x80000001, 0, ECX, 11, xop, Extended operation support
0x80000001, 0, ECX, 12, skinit, SKINIT and STGI support
0x80000001, 0, ECX, 13, wdt, Watchdog timer support
0x80000001, 0, ECX, 15, lwp, Lightweight profiling support
0x80000001, 0, ECX, 16, fma4, Four-operand FMA instruction support
0x80000001, 0, ECX, 17, tce, Translation cache extension
0x80000001, 0, ECX, 22, TopologyExtensions, Indicates support for Core::X86::Cpuid::CachePropEax0 and Core::X86::Cpuid::ExtApicId
0x80000001, 0, ECX, 23, perfctrextcore, Indicates support for Core::X86::Msr::PERF_CTL0 - 5 and Core::X86::Msr::PERF_CTR
0x80000001, 0, ECX, 24, perfctrextdf, Indicates support for Core::X86::Msr::DF_PERF_CTL and Core::X86::Msr::DF_PERF_CTR
0x80000001, 0, ECX, 26, databreakpointextension, Indicates data breakpoint support for Core::X86::Msr::DR0_ADDR_MASK, Core::X86::Msr::DR1_ADDR_MASK, Core::X86::Msr::DR2_ADDR_MASK and Core::X86::Msr::DR3_ADDR_MASK
0x80000001, 0, ECX, 27, perftsc, Performance time-stamp counter supported
0x80000001, 0, ECX, 28, perfctrextllc, Indicates support for L3 performance counter extensions
0x80000001, 0, ECX, 29, mwaitextended, MWAITX and MONITORX capability is supported
0x80000001, 0, ECX, 30, admskextn, Indicates support for address mask extension (to 32 bits and to all 4 DRs) for instruction breakpoints
0x80000001, 0, EDX, 0, fpu, x87 floating point unit on-chip
0x80000001, 0, EDX, 1, vme, Virtual-mode enhancements
0x80000001, 0, EDX, 2, de, Debugging extensions, IO breakpoints, CR4.DE
0x80000001, 0, EDX, 3, pse, Page-size extensions (4 MB pages)
0x80000001, 0, EDX, 4, tsc, Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD
0x80000001, 0, EDX, 5, msr, Model-specific registers (MSRs), with RDMSR and WRMSR instructions
0x80000001, 0, EDX, 6, pae, Physical-address extensions (PAE)
0x80000001, 0, EDX, 7, mce, Machine Check Exception, CR4.MCE
0x80000001, 0, EDX, 8, cmpxchg8b, CMPXCHG8B instruction
0x80000001, 0, EDX, 9, apic, advanced programmable interrupt controller (APIC) exists and is enabled
0x80000001, 0, EDX, 11, sysret, SYSCALL/SYSRET supported
0x80000001, 0, EDX, 12, mtrr, Memory-type range registers
0x80000001, 0, EDX, 13, pge, Page global extension, CR4.PGE
0x80000001, 0, EDX, 14, mca, Machine check architecture, MCG_CAP
0x80000001, 0, EDX, 15, cmov, Conditional move instructions, CMOV, FCOMI, FCMOV
0x80000001, 0, EDX, 16, pat, Page attribute table
0x80000001, 0, EDX, 17, pse36, Page-size extensions
0x80000001, 0, EDX, 20, exec_dis, Execute Disable Bit available
0x80000001, 0, EDX, 22, mmxext, AMD extensions to MMX instructions
0x80000001, 0, EDX, 23, mmx, MMX instructions
0x80000001, 0, EDX, 24, fxsr, FXSAVE and FXRSTOR instructions
0x80000001, 0, EDX, 25, ffxsr, FXSAVE and FXRSTOR instruction optimizations
0x80000001, 0, EDX, 26, 1gb_page, 1GB page supported
0x80000001, 0, EDX, 27, rdtscp, RDTSCP and IA32_TSC_AUX are available
#0x80000001, 0, EDX, 29, 64b, 64b Architecture supported
0x80000001, 0, EDX, 29, lm, 64b Architecture supported
0x80000001, 0, EDX, 30, threednowext, AMD extensions to 3DNow! instructions
0x80000001, 0, EDX, 31, threednow, 3DNow! instructions
# Leaf 80000002H/80000003H/80000004H
# Processor Brand String
1 # The basic row format is:
184 #
185 # Leaf 08H
186 #
187 # Leaf 09H
188 # Direct Cache Access (DCA) information
189
190 # Leaf 0AH
191 # Architectural Performance Monitoring
340 0x80000001, 0, EDX, 25, ffxsr, FXSAVE and FXRSTOR instruction optimizations
341 0x80000001, 0, EDX, 26, 1gb_page, 1GB page supported
342 0x80000001, 0, EDX, 27, rdtscp, RDTSCP and IA32_TSC_AUX are available
343 0x80000001, 0, EDX, 29, lm, 64b Architecture supported
344 0x80000001, 0, EDX, 30, threednowext, AMD extensions to 3DNow! instructions
345 0x80000001, 0, EDX, 31, threednow, 3DNow! instructions
346 # Leaf 80000002H/80000003H/80000004H
347 # Processor Brand String
348 # Leaf 80000005H
349 # Reserved
350 # Leaf 80000006H
351 # Extended L2 Cache Features
352 0x80000006, 0, ECX, 7:0, clsize, Cache Line size in bytes
353 0x80000006, 0, ECX, 15:12, l2c_assoc, L2 Associativity
354 0x80000006, 0, ECX, 31:16, csize, Cache size in 1K units
355 # Leaf 80000007H
356 0x80000007, 0, EDX, 8, nonstop_tsc, Invariant TSC available
357 # Leaf 80000008H
358 0x80000008, 0, EAX, 7:0, phy_adr_bits, Physical Address Bits
359 0x80000008, 0, EAX, 15:8, lnr_adr_bits, Linear Address Bits
360 0x80000007, 0, EBX, 9, wbnoinvd, WBNOINVD
361 # 0x8000001E
362 # EAX: Extended APIC ID
363 0x8000001E,
364 # EBX: Core Identifiers
365 0x8000001E,
366 0x8000001E,
367 # ECX: Node Identifiers
368 0x8000001E,
369 0x8000001E,
370 # 8000001F: AMD Secure Encryption
371 0x8000001F,
372 0x8000001F,
373 0x8000001F,
374 0x8000001F,
375 0x8000001F,
376 0x8000001F,
377 0x8000001F,
378 0x8000001F,
379
380
381
382
383
384
385
386
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32
tools/arch/x86/kcpuid/kcpuid.c
View File

@@ -33,7 +33,7 @@ struct reg_desc {
struct bits_desc descs[32];
};
enum {
enum cpuid_reg {
R_EAX = 0,
R_EBX,
R_ECX,
@@ -41,6 +41,10 @@ enum {
NR_REGS
};
static const char * const reg_names[] = {
"EAX", "EBX", "ECX", "EDX",
};
struct subleaf {
u32 index;
u32 sub;
@@ -428,12 +432,18 @@ static void parse_text(void)
/* Decode every eax/ebx/ecx/edx */
static void decode_bits(u32 value, struct reg_desc *rdesc)
static void decode_bits(u32 value, struct reg_desc *rdesc, enum cpuid_reg reg)
{
struct bits_desc *bdesc;
int start, end, i;
u32 mask;
if (!rdesc->nr) {
if (show_details)
printf("\t %s: 0x%08x\n", reg_names[reg], value);
return;
}
for (i = 0; i < rdesc->nr; i++) {
bdesc = &rdesc->descs[i];
@@ -468,13 +478,21 @@ static void show_leaf(struct subleaf *leaf)
if (!leaf)
return;
if (show_raw)
if (show_raw) {
leaf_print_raw(leaf);
} else {
if (show_details)
printf("CPUID_0x%x_ECX[0x%x]:\n",
leaf->index, leaf->sub);
}
decode_bits(leaf->eax, &leaf->info[R_EAX]);
decode_bits(leaf->ebx, &leaf->info[R_EBX]);
decode_bits(leaf->ecx, &leaf->info[R_ECX]);
decode_bits(leaf->edx, &leaf->info[R_EDX]);
decode_bits(leaf->eax, &leaf->info[R_EAX], R_EAX);
decode_bits(leaf->ebx, &leaf->info[R_EBX], R_EBX);
decode_bits(leaf->ecx, &leaf->info[R_ECX], R_ECX);
decode_bits(leaf->edx, &leaf->info[R_EDX], R_EDX);
if (!show_raw && show_details)
printf("\n");
}
static void show_func(struct cpuid_func *func)