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phy: exynos5-usbdrd: support SS combo phy for ExynosAutov920
Update phy driver to enable SS combo phy for this SoC. New registers' definitions, phy ops (init/exit), and dedicated phy driver data structure are added for SS combo phy. Add these changes in the driver to support SS combo phy for this SoC. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com> Link: https://patch.msgid.link/20251124110453.2887437-7-pritam.sutar@samsung.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Pritam Manohar Sutar
committed by
Vinod Koul
Vinod Koul
parent
05681c9c7e
commit
2fdfc1bb75
@@ -273,6 +273,36 @@
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#define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110
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#define HSPPLLTUNE_FSEL GENMASK(18, 16)
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/* ExynosAutov920 phy usb31drd port reg */
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#define EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL 0x000
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#define PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN BIT(5)
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#define PHY_RST_CTRL_PIPE_LANE0_RESET_N BIT(4)
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#define PHY_RST_CTRL_PHY_RESET_OVRD_EN BIT(1)
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#define PHY_RST_CTRL_PHY_RESET BIT(0)
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#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0 0x0004
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#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR GENMASK(31, 16)
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#define PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK BIT(8)
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#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK BIT(4)
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#define PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL BIT(0)
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#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1 0x0008
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#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2 0x000c
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#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN BIT(0)
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#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA GENMASK(31, 16)
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#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0 0x100
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#define PHY_CONFIG0_PHY0_PMA_PWR_STABLE BIT(14)
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#define PHY_CONFIG0_PHY0_PCS_PWR_STABLE BIT(13)
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#define PHY_CONFIG0_PHY0_ANA_PWR_EN BIT(1)
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#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7 0x11c
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#define PHY_CONFIG7_PHY_TEST_POWERDOWN BIT(24)
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#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4 0x110
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#define PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN BIT(2)
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/* Exynos9 - GS101 */
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#define EXYNOS850_DRD_SECPMACTL 0x48
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#define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12)
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@@ -2077,6 +2107,251 @@ static const struct exynos5_usbdrd_phy_drvdata exynos990_usbdrd_phy = {
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.n_regulators = ARRAY_SIZE(exynos5_regulator_names),
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};
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static void
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exynosautov920_usb31drd_cr_clk(struct exynos5_usbdrd_phy *phy_drd, bool high)
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{
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void __iomem *reg_phy = phy_drd->reg_phy;
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u32 reg;
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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if (high)
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reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK;
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else
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reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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fsleep(1);
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}
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static void
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exynosautov920_usb31drd_port_phy_ready(struct exynos5_usbdrd_phy *phy_drd)
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{
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struct device *dev = phy_drd->dev;
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void __iomem *reg_phy = phy_drd->reg_phy;
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static const unsigned int timeout_us = 20000;
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static const unsigned int sleep_us = 40;
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u32 reg;
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int err;
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/* Clear cr_para_con */
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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reg &= ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK |
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PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR);
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reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1);
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writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
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exynosautov920_usb31drd_cr_clk(phy_drd, true);
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exynosautov920_usb31drd_cr_clk(phy_drd, false);
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/*
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* The maximum time from phy reset de-assertion to de-assertion of
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* tx/rx_ack can be as high as 5ms in fast simulation mode.
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* Time to phy ready is < 20ms
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*/
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err = readl_poll_timeout(reg_phy +
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EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0,
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reg, !(reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK),
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sleep_us, timeout_us);
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if (err)
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dev_err(dev, "timed out waiting for rx/tx_ack: %#.8x\n", reg);
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reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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}
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static void
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exynosautov920_usb31drd_cr_write(struct exynos5_usbdrd_phy *phy_drd,
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u16 addr, u16 data)
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{
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void __iomem *reg_phy = phy_drd->reg_phy;
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u32 cnt = 0;
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u32 reg;
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/* Pre Clocking */
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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/*
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* tx clks must be available prior to assertion of tx req.
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* tx pstate p2 to p0 transition directly is not permitted.
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* tx clk ready must be asserted synchronously on tx clk prior
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* to internal transmit clk alignment sequence in the phy
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* when entering from p2 to p1 to p0.
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*/
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do {
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exynosautov920_usb31drd_cr_clk(phy_drd, true);
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exynosautov920_usb31drd_cr_clk(phy_drd, false);
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cnt++;
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} while (cnt < 15);
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reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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/*
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* tx data path is active when tx lane is in p0 state
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* and tx data en asserted. enable cr_para_wr_en.
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*/
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
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reg &= ~PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA;
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reg |= FIELD_PREP(PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA, data) |
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PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
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/* write addr */
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR;
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reg |= FIELD_PREP(PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR, addr) |
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PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK |
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PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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/* check cr_para_ack*/
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cnt = 0;
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do {
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/*
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* data symbols are captured by phy on rising edge of the
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* tx_clk when tx data enabled.
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* completion of the write cycle is acknowledged by assertion
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* of the cr_para_ack.
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*/
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exynosautov920_usb31drd_cr_clk(phy_drd, true);
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
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if ((reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK))
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break;
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exynosautov920_usb31drd_cr_clk(phy_drd, false);
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/*
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* wait for minimum of 10 cr_para_clk cycles after phy reset
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* is negated, before accessing control regs to allow for
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* internal resets.
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*/
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cnt++;
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} while (cnt < 10);
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if (cnt < 10)
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exynosautov920_usb31drd_cr_clk(phy_drd, false);
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}
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static void
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exynosautov920_usb31drd_phy_reset(struct exynos5_usbdrd_phy *phy_drd, int val)
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{
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void __iomem *reg_phy = phy_drd->reg_phy;
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u32 reg;
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
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reg &= ~PHY_RST_CTRL_PHY_RESET_OVRD_EN;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
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if (val)
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reg |= PHY_RST_CTRL_PHY_RESET;
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else
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reg &= ~PHY_RST_CTRL_PHY_RESET;
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reg |= PHY_RST_CTRL_PHY_RESET_OVRD_EN;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
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}
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static void
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exynosautov920_usb31drd_lane0_reset(struct exynos5_usbdrd_phy *phy_drd, int val)
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{
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void __iomem *reg_phy = phy_drd->reg_phy;
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u32 reg;
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
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reg |= PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
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if (val)
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reg &= ~PHY_RST_CTRL_PIPE_LANE0_RESET_N;
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else
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reg |= PHY_RST_CTRL_PIPE_LANE0_RESET_N;
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reg &= ~PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
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}
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static void
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exynosautov920_usb31drd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
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{
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void __iomem *reg_phy = phy_drd->reg_phy;
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u32 reg;
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/*
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* Phy and Pipe Lane reset assert.
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* assert reset (phy_reset = 1).
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* The lane-ack outputs are asserted during reset (tx_ack = rx_ack = 1)
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*/
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exynosautov920_usb31drd_phy_reset(phy_drd, 1);
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exynosautov920_usb31drd_lane0_reset(phy_drd, 1);
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/*
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* ANA Power En, PCS & PMA PWR Stable Set
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* ramp-up power suppiles
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*/
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0);
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reg |= PHY_CONFIG0_PHY0_ANA_PWR_EN | PHY_CONFIG0_PHY0_PCS_PWR_STABLE |
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PHY_CONFIG0_PHY0_PMA_PWR_STABLE;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0);
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fsleep(10);
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/*
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* phy is not functional in test_powerdown mode, test_powerdown to be
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* de-asserted for normal operation
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*/
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7);
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reg &= ~PHY_CONFIG7_PHY_TEST_POWERDOWN;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7);
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/*
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* phy reset signal be asserted for minimum 10us after power
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* supplies are ramped-up
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*/
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fsleep(10);
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/*
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* Phy and Pipe Lane reset assert de-assert
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*/
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exynosautov920_usb31drd_phy_reset(phy_drd, 0);
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exynosautov920_usb31drd_lane0_reset(phy_drd, 0);
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/* Pipe_rx0_sris_mode_en = 1 */
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4);
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reg |= PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4);
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/*
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* wait for lane ack outputs to de-assert (tx_ack = rx_ack = 0)
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* Exit from the reset state is indicated by de-assertion of *_ack
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*/
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exynosautov920_usb31drd_port_phy_ready(phy_drd);
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/* override values for level settings */
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exynosautov920_usb31drd_cr_write(phy_drd, 0x22, 0x00F5);
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}
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static void
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exynosautov920_usb31drd_ssphy_disable(struct exynos5_usbdrd_phy *phy_drd)
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{
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void __iomem *reg_phy = phy_drd->reg_phy;
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u32 reg;
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/* 1. Assert reset (phy_reset = 1) */
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exynosautov920_usb31drd_lane0_reset(phy_drd, 1);
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exynosautov920_usb31drd_phy_reset(phy_drd, 1);
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/* phy test power down */
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reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7);
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reg |= PHY_CONFIG7_PHY_TEST_POWERDOWN;
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writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7);
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}
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static void
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exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
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{
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@@ -2172,12 +2447,15 @@ exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
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/* after POR low and delay 75us, PHYCLOCK is guaranteed. */
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fsleep(75);
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/* force pipe3 signal for link */
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/* Disable forcing pipe interface */
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reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL);
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reg |= LINKCTRL_FORCE_PIPE_EN;
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reg &= ~LINKCTRL_FORCE_PHYSTATUS;
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reg |= LINKCTRL_FORCE_RXELECIDLE;
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reg &= ~LINKCTRL_FORCE_PIPE_EN;
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writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL);
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/* Pclk to pipe_clk */
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reg = readl(reg_phy + EXYNOS2200_DRD_CLKRST);
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reg |= EXYNOS2200_CLKRST_LINK_PCLK_SEL;
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writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST);
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}
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static void
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@@ -2264,6 +2542,8 @@ static int exynosautov920_usbdrd_combo_phy_exit(struct phy *phy)
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if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
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exynosautov920_usbdrd_hsphy_disable(phy_drd);
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else if (inst->phy_cfg->id == EXYNOS5_DRDPHY_PIPE3)
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exynosautov920_usb31drd_ssphy_disable(phy_drd);
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/* enable PHY isol */
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inst->phy_cfg->phy_isol(inst, true);
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@@ -2320,10 +2600,44 @@ static int exynosautov920_usbdrd_phy_power_off(struct phy *phy)
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return 0;
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}
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static const char * const exynosautov920_usb30_regulators[] = {
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"dvdd", "vdd18",
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};
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static const char * const exynosautov920_usb20_regulators[] = {
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"dvdd", "vdd18", "vdd33",
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};
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static const struct
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exynos5_usbdrd_phy_config usb31drd_phy_cfg_exynosautov920[] = {
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{
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.id = EXYNOS5_DRDPHY_PIPE3,
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.phy_isol = exynos5_usbdrd_phy_isol,
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.phy_init = exynosautov920_usb31drd_pipe3_init,
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},
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};
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static const struct phy_ops exynosautov920_usb31drd_combo_ssphy_ops = {
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.init = exynosautov920_usbdrd_phy_init,
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.exit = exynosautov920_usbdrd_combo_phy_exit,
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.power_on = exynosautov920_usbdrd_phy_power_on,
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.power_off = exynosautov920_usbdrd_phy_power_off,
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.owner = THIS_MODULE,
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};
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static const
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struct exynos5_usbdrd_phy_drvdata exynosautov920_usb31drd_combo_ssphy = {
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.phy_cfg = usb31drd_phy_cfg_exynosautov920,
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.phy_ops = &exynosautov920_usb31drd_combo_ssphy_ops,
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.pmu_offset_usbdrd0_phy = EXYNOSAUTOV920_PHY_CTRL_USB31,
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.clk_names = exynos5_clk_names,
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.n_clks = ARRAY_SIZE(exynos5_clk_names),
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.core_clk_names = exynos5_core_clk_names,
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.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
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.regulator_names = exynosautov920_usb30_regulators,
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.n_regulators = ARRAY_SIZE(exynosautov920_usb30_regulators),
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};
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static const struct phy_ops exynosautov920_usbdrd_combo_hsphy_ops = {
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.init = exynosautov920_usbdrd_phy_init,
|
||||
.exit = exynosautov920_usbdrd_combo_phy_exit,
|
||||
@@ -2588,6 +2902,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
|
||||
}, {
|
||||
.compatible = "samsung,exynos990-usbdrd-phy",
|
||||
.data = &exynos990_usbdrd_phy
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov920-usb31drd-combo-ssphy",
|
||||
.data = &exynosautov920_usb31drd_combo_ssphy
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov920-usbdrd-combo-hsphy",
|
||||
.data = &exynosautov920_usbdrd_combo_hsphy
|
||||
|
||||
@@ -1017,4 +1017,5 @@
|
||||
|
||||
/* exynosautov920 */
|
||||
#define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710)
|
||||
#define EXYNOSAUTOV920_PHY_CTRL_USB31 (0x0714)
|
||||
#endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */
|
||||
|
||||
Reference in New Issue
Block a user