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drm/i915/pfit: split out intel_pfit_regs.h
Split out the panel fitter registers to a separate file. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/db8952baa3e3e5eaaa8a3a5bc723c4e47aeaa6a7.1740564009.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
@@ -53,6 +53,7 @@
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#include "intel_lvds_regs.h"
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#include "intel_panel.h"
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#include "intel_pfit.h"
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#include "intel_pfit_regs.h"
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#include "intel_pps_regs.h"
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/* Private structure for the integrated LVDS support */
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@@ -42,6 +42,7 @@
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#include "intel_frontbuffer.h"
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#include "intel_overlay.h"
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#include "intel_pci_config.h"
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#include "intel_pfit_regs.h"
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/* Limits for overlay size. According to intel doc, the real limits are:
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* Y width: 4095, UV width (planar): 2047, Y height: 2047,
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@@ -11,6 +11,7 @@
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#include "intel_display_types.h"
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#include "intel_lvds_regs.h"
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#include "intel_pfit.h"
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#include "intel_pfit_regs.h"
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static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
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{
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79
drivers/gpu/drm/i915/display/intel_pfit_regs.h
Normal file
79
drivers/gpu/drm/i915/display/intel_pfit_regs.h
Normal file
@@ -0,0 +1,79 @@
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/* SPDX-License-Identifier: MIT */
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/* Copyright © 2025 Intel Corporation */
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#ifndef __INTEL_PFIT_REGS_H__
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#define __INTEL_PFIT_REGS_H__
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#include "intel_display_reg_defs.h"
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/* Panel fitting */
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#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
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#define PFIT_ENABLE REG_BIT(31)
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#define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
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#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
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#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
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#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
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#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1)
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#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2)
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#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3)
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#define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
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#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
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#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
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#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
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#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
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#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)
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#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
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#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
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#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)
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#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
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#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
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#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
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#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
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#define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
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#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
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#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))
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#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
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#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
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#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
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/* CPU panel fitter */
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/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
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#define _PFA_CTL_1 0x68080
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#define _PFB_CTL_1 0x68880
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#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
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#define PF_ENABLE REG_BIT(31)
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#define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
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#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))
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#define PF_FILTER_MASK REG_GENMASK(24, 23)
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#define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0)
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#define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1)
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#define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)
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#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
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#define _PFA_WIN_SZ 0x68074
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#define _PFB_WIN_SZ 0x68874
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#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
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#define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
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#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
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#define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
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#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
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#define _PFA_WIN_POS 0x68070
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#define _PFB_WIN_POS 0x68870
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#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
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#define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
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#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
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#define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
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#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
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#define _PFA_VSCALE 0x68084
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#define _PFB_VSCALE 0x68884
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#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
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#define _PFA_HSCALE 0x68090
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#define _PFB_HSCALE 0x68890
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#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
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#endif /* __INTEL_PFIT_REGS_H__ */
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@@ -1385,38 +1385,6 @@
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/* ADL and later: */
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#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
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/* Panel fitting */
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#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
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#define PFIT_ENABLE REG_BIT(31)
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#define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
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#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
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#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
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#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
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#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1)
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#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2)
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#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3)
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#define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
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#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
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#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
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#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
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#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
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#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)
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#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
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#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
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#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)
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#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
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#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
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#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
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#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
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#define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
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#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
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#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))
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#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
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#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
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#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
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#define PCH_GTC_CTL _MMIO(0xe7000)
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#define PCH_GTC_ENABLE (1 << 31)
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@@ -1911,44 +1879,6 @@
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#define _PIPEB_LINK_N2 0x6104c
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#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
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/* CPU panel fitter */
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/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
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#define _PFA_CTL_1 0x68080
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#define _PFB_CTL_1 0x68880
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#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
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#define PF_ENABLE REG_BIT(31)
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#define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
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#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))
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#define PF_FILTER_MASK REG_GENMASK(24, 23)
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#define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0)
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#define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1)
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#define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)
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#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
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#define _PFA_WIN_SZ 0x68074
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#define _PFB_WIN_SZ 0x68874
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#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
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#define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
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#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
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#define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
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#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
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#define _PFA_WIN_POS 0x68070
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#define _PFB_WIN_POS 0x68870
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#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
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#define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
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#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
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#define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
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#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
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#define _PFA_VSCALE 0x68084
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#define _PFB_VSCALE 0x68884
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#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
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#define _PFA_HSCALE 0x68090
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#define _PFB_HSCALE 0x68890
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#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
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/*
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* Skylake scalers
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*/
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@@ -18,6 +18,7 @@
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#include "display/intel_fbc_regs.h"
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#include "display/intel_fdi_regs.h"
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#include "display/intel_lvds_regs.h"
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#include "display/intel_pfit_regs.h"
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#include "display/intel_psr_regs.h"
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#include "display/intel_sprite_regs.h"
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#include "display/skl_universal_plane_regs.h"
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