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drm/i915/vrr: Pause DC Balancing for DSB commits

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Pause the DMC DC Balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.

--v2:
- Remove typo. (Ankit)
- Separate vrr enable structuring. (Ankit)

--v3:
- Add gaurd before accessing DC balance bits.
- Remove redundancy checks.

--v4:
- Move events to separate function.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-17-mitulkumar.ajitkumar.golani@intel.com
This commit is contained in:
Ville Syrjälä
2025-12-23 16:15:38 +05:30
committed by Ankit Nautiyal
parent 27a4250ca2
commit 192bc98c6f
2 changed files with 22 additions and 0 deletions
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19
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -7330,6 +7330,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
if (new_crtc_state->use_flipq)
intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc);
if (new_crtc_state->vrr.dc_balance.enable) {
/*
* Pause the DMC DC balancing for the remainder of
* the commit so that vmin/vmax won't change after
* we've baked them into the DSB vblank evasion
* commands.
*
* FIXME maybe need a small delay here to make sure
* DMC has finished updating the values? Or we need
* a better DMC<->driver protocol that gives is real
* guarantees about that...
*/
intel_pipedmc_dcb_disable(NULL, crtc);
}
if (intel_crtc_needs_color_update(new_crtc_state))
intel_color_commit_noarm(new_crtc_state->dsb_commit,
new_crtc_state);
@@ -7383,6 +7398,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit);
intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
new_crtc_state);
if (new_crtc_state->vrr.dc_balance.enable)
intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
intel_dsb_interrupt(new_crtc_state->dsb_commit);
}

3
drivers/gpu/drm/i915/display/intel_vrr.c
View File

@@ -10,6 +10,7 @@
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dmc.h"
#include "intel_dmc_regs.h"
#include "intel_dp.h"
#include "intel_psr.h"
@@ -824,6 +825,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
crtc_state->vrr.dc_balance.vblank_target);
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
ADAPTIVE_SYNC_COUNTER_EN);
intel_pipedmc_dcb_enable(NULL, crtc);
}
static void
@@ -837,6 +839,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->vrr.dc_balance.enable)
return;
intel_pipedmc_dcb_disable(NULL, crtc);
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);