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Merge tag 'stm32-dt-for-v6.11-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt

Browse Source 
STM32 DT for v6.11, round 1

Highlights:
----------

-MCU:
  - Add syscfg missing clock on stm32f429.

- MPU:
  - STM32MP13:
    - Add camera support on stm32mp135f-dk bord using DCMIPP and
      GC2145 sensor.
    - Document PWM output for stm32mp135f-dk
    - Add goodix touchscreen support on stm32mp135f-dk board.
    - Add new DH DHCOR / DHSBC board (Som + carrier board) based on
      STM32MP135F SoC.
      SOM part contains: STM32MP135F SoC, 512MB DDR2L RAM and
      eMMC/SDIO wifi module.
      The carrier boards embedds 2 RGMII ETH ports, USB-A,USB-C
      and an extansion connector.
    - Add Ethernet controller support on stm32mp135f-dk.
      It uses LAN8742A PHY based on RMII.

  - STMP32MP15:
    - Rework Octavo OSD32MP1 split for USB phy.
    - Add OP-TEE IRQ for asynchronous notification support.
      It allows OP-TEE to trig Linux.

  - STM32MP25:
    - Add OP-TEE IRQ for asynchronous notification support.
      It allows OP-TEE to trig Linux.
    - Enable firewall for RCC.
    - Add all U(s)ART nodes for stm32mp25.
    - Add 3 power domains for low power modes.
    - Add HPDMA support.
    - Add Ethernet controller (ETH2) support on stm32mp257f-ev1.
      It uses Realtek PHY based on RGMII.
    - Add and enable SCMI regulator support.

* tag 'stm32-dt-for-v6.11-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (31 commits)
  arm64: dts: st: describe power supplies for stm32mp257f-ev1 board
  arm64: dts: st: add scmi regulators on stm32mp25
  regulator: Add STM32MP25 regulator bindings
  ARM: dts: stm32: omit unused pinctrl groups from stm32mp13 dtb files
  arm64: dts: st: enable Ethernet2 on stm32mp257f-ev1 board
  arm64: dts: st: add eth2 pinctrl entries in stm32mp25-pinctrl.dtsi
  arm64: dts: st: add ethernet1 and ethernet2 support on stm32mp25
  arm64: dts: st: add HPDMA nodes on stm32mp251
  ARM: dts: stm32: Add ethernet support for DH STM32MP13xx DHCOR DHSBC board
  ARM: dts: stm32: order stm32mp13-pinctrl nodes
  ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
  ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
  ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
  ARM: dts: stm32: Document output pins for PWMs on stm32mp135f-dk
  ARM: dts: stm32: OP-TEE async notif interrupt for ST STM32MP15x boards
  ARM: dts: stm32: Missing clocks for stm32f429's syscfg.
  ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board
  ARM: dts: stm32: Add pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board
  dt-bindings: arm: stm32: Add compatible string for DH electronics STM32MP13xx DHCOR DHSBC board
  ARM: dts: stm32: osd32: move pwr_regulators to common
  ...

Link: https://lore.kernel.org/r/8f10bd29-d067-4060-89ff-2e1a605f3141@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-07-08 16:33:02 +02:00
parent a9fe0720f2 419ed754a3
commit 03b4edd51f
22 changed files with 2146 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
View File

@@ -59,6 +59,12 @@ properties:
- prt,prtt1s # Protonic PRTT1S
- const: st,stm32mp151
- description: DH STM32MP135 DHCOR SoM based Boards
items:
- const: dh,stm32mp135f-dhcor-dhsbc
- const: dh,stm32mp135f-dhcor-som
- const: st,stm32mp135
- description: DH STM32MP151 DHCOR SoM based Boards
items:
- const: dh,stm32mp151a-dhcor-testbench

1
arch/arm/boot/dts/st/Makefile
View File

@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32h743i-eval.dtb \
stm32h743i-disco.dtb \
stm32h750i-art-pi.dtb \
stm32mp135f-dhcor-dhsbc.dtb \
stm32mp135f-dk.dtb \
stm32mp151a-prtt1a.dtb \
stm32mp151a-prtt1c.dtb \

1
arch/arm/boot/dts/st/stm32f429.dtsi
View File

@@ -579,6 +579,7 @@
syscfg: syscon@40013800 {
compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>;
};
exti: interrupt-controller@40013c00 {

697
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
View File

@@ -6,6 +6,14 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
/omit-if-no-ref/
adc1_pins_a: adc1-pins-0 {
pins {
pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
};
};
/omit-if-no-ref/
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
@@ -13,6 +21,241 @@
};
};
/omit-if-no-ref/
adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
pins {
pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */
<STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */
};
};
/omit-if-no-ref/
dcmipp_pins_a: dcmi-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
<STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */
<STM32_PINMUX('B', 7, AF14)>,/* DCMI_PIXCLK */
<STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
<STM32_PINMUX('D', 0, AF13)>,/* DCMI_D1 */
<STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */
<STM32_PINMUX('E', 4, AF13)>,/* DCMI_D3 */
<STM32_PINMUX('D', 11, AF14)>,/* DCMI_D4 */
<STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
<STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
<STM32_PINMUX('E', 14, AF13)>;/* DCMI_D7 */
bias-disable;
};
};
/omit-if-no-ref/
dcmipp_sleep_pins_a: dcmi-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
<STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */
<STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_PIXCLK */
<STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
<STM32_PINMUX('D', 0, ANALOG)>,/* DCMI_D1 */
<STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */
<STM32_PINMUX('E', 4, ANALOG)>,/* DCMI_D3 */
<STM32_PINMUX('D', 11, ANALOG)>,/* DCMI_D4 */
<STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
<STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
<STM32_PINMUX('E', 14, ANALOG)>;/* DCMI_D7 */
};
};
/omit-if-no-ref/
eth1_rgmii_pins_a: eth1-rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
<STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
bias-disable;
};
};
/omit-if-no-ref/
eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */
<STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */
};
};
/omit-if-no-ref/
eth1_rmii_pins_a: eth1-rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */
<STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */
bias-disable;
};
};
/omit-if-no-ref/
eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */
<STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */
};
};
/omit-if-no-ref/
eth2_rgmii_pins_a: eth2-rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */
<STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */
bias-disable;
};
};
/omit-if-no-ref/
eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('G', 1, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 6, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('G', 3, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('B', 6, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('A', 8, ANALOG)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */
<STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */
};
};
/omit-if-no-ref/
eth2_rmii_pins_a: eth2-rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */
<STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */
<STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */
bias-disable;
};
};
/omit-if-no-ref/
eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */
<STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */
<STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */
};
};
/omit-if-no-ref/
goodix_pins_a: goodix-0 {
/*
* touchscreen reset needs to be configured
* via the pinctrl not the driver (a pull-down resistor
* has been soldered onto the reset line which forces
* the touchscreen to reset state).
*/
pins1 {
pinmux = <STM32_PINMUX('H', 2, GPIO)>;
output-high;
bias-pull-up;
};
/*
* Interrupt line must have a pull-down resistor
* in order to freeze the i2c address at 0x5D
*/
pins2 {
pinmux = <STM32_PINMUX('F', 5, GPIO)>;
bias-pull-down;
};
};
/omit-if-no-ref/
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@@ -23,6 +266,7 @@
};
};
/omit-if-no-ref/
i2c1_sleep_pins_a: i2c1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
@@ -30,6 +274,7 @@
};
};
/omit-if-no-ref/
i2c5_pins_a: i2c5-0 {
pins {
pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
@@ -40,6 +285,7 @@
};
};
/omit-if-no-ref/
i2c5_sleep_pins_a: i2c5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
@@ -47,6 +293,26 @@
};
};
/omit-if-no-ref/
i2c5_pins_b: i2c5-1 {
pins {
pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
<STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
/omit-if-no-ref/
i2c5_sleep_pins_b: i2c5-sleep-1 {
pins {
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
<STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */
};
};
/omit-if-no-ref/
ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
@@ -77,6 +343,7 @@
};
};
/omit-if-no-ref/
ltdc_sleep_pins_a: ltdc-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
@@ -104,6 +371,51 @@
};
};
/omit-if-no-ref/
m_can1_pins_a: m-can1-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
bias-disable;
};
};
/omit-if-no-ref/
m_can1_sleep_pins_a: m_can1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */
<STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */
};
};
/omit-if-no-ref/
m_can2_pins_a: m-can2-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */
bias-disable;
};
};
/omit-if-no-ref/
m_can2_sleep_pins_a: m_can2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */
<STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */
};
};
/omit-if-no-ref/
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, GPIO)>;
@@ -111,6 +423,7 @@
};
};
/omit-if-no-ref/
pwm3_pins_a: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
@@ -120,12 +433,14 @@
};
};
/omit-if-no-ref/
pwm3_sleep_pins_a: pwm3-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
};
};
/omit-if-no-ref/
pwm4_pins_a: pwm4-0 {
pins {
pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
@@ -135,12 +450,31 @@
};
};
/omit-if-no-ref/
pwm4_sleep_pins_a: pwm4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
};
};
/omit-if-no-ref/
pwm5_pins_a: pwm5-0 {
pins {
pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
/omit-if-no-ref/
pwm5_sleep_pins_a: pwm5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */
};
};
/omit-if-no-ref/
pwm8_pins_a: pwm8-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
@@ -150,12 +484,31 @@
};
};
/omit-if-no-ref/
pwm8_sleep_pins_a: pwm8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
};
};
/omit-if-no-ref/
pwm13_pins_a: pwm13-0 {
pins {
pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
/omit-if-no-ref/
pwm13_sleep_pins_a: pwm13-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */
};
};
/omit-if-no-ref/
pwm14_pins_a: pwm14-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
@@ -165,12 +518,107 @@
};
};
/omit-if-no-ref/
pwm14_sleep_pins_a: pwm14-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
};
};
/omit-if-no-ref/
qspi_clk_pins_a: qspi-clk-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
};
/omit-if-no-ref/
qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
};
};
/omit-if-no-ref/
qspi_bk1_pins_a: qspi-bk1-0 {
pins {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
};
/omit-if-no-ref/
qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */
};
};
/omit-if-no-ref/
qspi_cs1_pins_a: qspi-cs1-0 {
pins {
pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
};
};
/omit-if-no-ref/
qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */
};
};
/omit-if-no-ref/
sai1a_pins_a: sai1a-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
<STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */
<STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */
slew-rate = <0>;
drive-push-pull;
bias-disable;
};
};
/omit-if-no-ref/
sai1a_sleep_pins_a: sai1a-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
<STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */
<STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */
};
};
/omit-if-no-ref/
sai1b_pins_a: sai1b-0 {
pins {
pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */
bias-disable;
};
};
/omit-if-no-ref/
sai1b_sleep_pins_a: sai1b-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */
};
};
/omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -184,6 +632,7 @@
};
};
/omit-if-no-ref/
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -202,6 +651,7 @@
};
};
/omit-if-no-ref/
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
@@ -213,6 +663,7 @@
};
};
/omit-if-no-ref/
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
pins {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
@@ -222,6 +673,7 @@
};
};
/omit-if-no-ref/
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
@@ -235,6 +687,7 @@
};
};
/omit-if-no-ref/
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
@@ -253,6 +706,7 @@
};
};
/omit-if-no-ref/
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
@@ -264,6 +718,7 @@
};
};
/omit-if-no-ref/
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
pins {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
@@ -273,6 +728,80 @@
};
};
/omit-if-no-ref/
sdmmc2_d47_pins_a: sdmmc2-d47-0 {
pins {
pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
<STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
/omit-if-no-ref/
sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
};
};
/omit-if-no-ref/
spi2_pins_a: spi2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */
<STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */
bias-disable;
};
};
/omit-if-no-ref/
spi2_sleep_pins_a: spi2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */
<STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */
<STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */
};
};
/omit-if-no-ref/
spi3_pins_a: spi3-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */
<STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */
bias-disable;
};
};
/omit-if-no-ref/
spi3_sleep_pins_a: spi3-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */
<STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */
<STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */
};
};
/omit-if-no-ref/
spi5_pins_a: spi5-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
@@ -288,6 +817,7 @@
};
};
/omit-if-no-ref/
spi5_sleep_pins_a: spi5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
@@ -296,6 +826,7 @@
};
};
/omit-if-no-ref/
stm32g0_intn_pins_a: stm32g0-intn-0 {
pins {
pinmux = <STM32_PINMUX('I', 2, GPIO)>;
@@ -303,6 +834,7 @@
};
};
/omit-if-no-ref/
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
@@ -316,6 +848,7 @@
};
};
/omit-if-no-ref/
uart4_idle_pins_a: uart4-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
@@ -326,6 +859,7 @@
};
};
/omit-if-no-ref/
uart4_sleep_pins_a: uart4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
@@ -333,6 +867,84 @@
};
};
/omit-if-no-ref/
uart4_pins_b: uart4-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-pull-up;
};
};
/omit-if-no-ref/
uart4_idle_pins_b: uart4-idle-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-pull-up;
};
};
/omit-if-no-ref/
uart4_sleep_pins_b: uart4-sleep-1 {
pins {
pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
};
};
/omit-if-no-ref/
uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */
<STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */
<STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */
bias-disable;
};
};
/omit-if-no-ref/
uart7_idle_pins_a: uart7-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
<STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
bias-disable;
};
};
/omit-if-no-ref/
uart7_sleep_pins_a: uart7-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
<STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */
<STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */
<STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
};
};
/omit-if-no-ref/
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
@@ -346,6 +958,7 @@
};
};
/omit-if-no-ref/
uart8_idle_pins_a: uart8-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
@@ -356,6 +969,7 @@
};
};
/omit-if-no-ref/
uart8_sleep_pins_a: uart8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
@@ -363,6 +977,7 @@
};
};
/omit-if-no-ref/
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
@@ -378,6 +993,7 @@
};
};
/omit-if-no-ref/
usart1_idle_pins_a: usart1-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
@@ -395,6 +1011,7 @@
};
};
/omit-if-no-ref/
usart1_sleep_pins_a: usart1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
@@ -404,6 +1021,40 @@
};
};
/omit-if-no-ref/
usart1_pins_b: usart1-1 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
bias-pull-up;
};
};
/omit-if-no-ref/
usart1_idle_pins_b: usart1-idle-1 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */
};
pins2 {
pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
bias-pull-up;
};
};
/omit-if-no-ref/
usart1_sleep_pins_b: usart1-sleep-1 {
pins {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */
};
};
/omit-if-no-ref/
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
@@ -419,6 +1070,7 @@
};
};
/omit-if-no-ref/
usart2_idle_pins_a: usart2-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
@@ -436,6 +1088,7 @@
};
};
/omit-if-no-ref/
usart2_sleep_pins_a: usart2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
@@ -444,4 +1097,48 @@
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
};
/omit-if-no-ref/
usart2_pins_b: usart2-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */
<STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
<STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */
bias-disable;
};
};
/omit-if-no-ref/
usart2_idle_pins_b: usart2-idle-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
bias-disable;
};
};
/omit-if-no-ref/
usart2_sleep_pins_b: usart2-sleep-1 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
<STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
};
};
};

38
arch/arm/boot/dts/st/stm32mp131.dtsi
View File

@@ -979,6 +979,12 @@
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
ethernet_mac1_address: mac1@e4 {
reg = <0xe4 0x6>;
};
ethernet_mac2_address: mac2@ea {
reg = <0xea 0x6>;
};
};
etzpc: bus@5c007000 {
@@ -1505,6 +1511,38 @@
status = "disabled";
};
ethernet1: ethernet@5800a000 {
compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
reg = <0x5800a000 0x2000>;
reg-names = "stmmaceth";
interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<&exti 68 1>;
interrupt-names = "macirq", "eth_wake_irq";
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
"ethstp",
"eth-ck";
clocks = <&rcc ETH1MAC>,
<&rcc ETH1TX>,
<&rcc ETH1RX>,
<&rcc ETH1STP>,
<&rcc ETH1CK_K>;
st,syscon = <&syscfg 0x4 0xff0000>;
snps,mixed-burst;
snps,pbl = <2>;
snps,axi-config = <&stmmac_axi_config_1>;
snps,tso;
access-controllers = <&etzpc 48>;
status = "disabled";
stmmac_axi_config_1: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <0x7>;
snps,wr_osr_lmt = <0x7>;
};
};
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;

31
arch/arm/boot/dts/st/stm32mp133.dtsi
View File

@@ -68,4 +68,35 @@
};
};
};
ethernet2: ethernet@5800e000 {
compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
reg = <0x5800e000 0x2000>;
reg-names = "stmmaceth";
interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
"ethstp",
"eth-ck";
clocks = <&rcc ETH2MAC>,
<&rcc ETH2TX>,
<&rcc ETH2RX>,
<&rcc ETH2STP>,
<&rcc ETH2CK_K>;
st,syscon = <&syscfg 0x4 0xff000000>;
snps,mixed-burst;
snps,pbl = <2>;
snps,axi-config = <&stmmac_axi_config_2>;
snps,tso;
access-controllers = <&etzpc 49>;
status = "disabled";
stmmac_axi_config_2: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <0x7>;
snps,wr_osr_lmt = <0x7>;
};
};
};

377
arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts Normal file
View File

@@ -0,0 +1,377 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2024 Marek Vasut <marex@denx.de>
*
* DHCOR STM32MP13 variant:
* DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
* DHCOR PCB number: 718-100 or newer
* DHSBC PCB number: 719-100 or newer
*/
/dts-v1/;
#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
#include "stm32mp13xx-dhcor-som.dtsi"
/ {
model = "DH electronics STM32MP135F DHCOR DHSBC";
compatible = "dh,stm32mp135f-dhcor-dhsbc",
"dh,stm32mp135f-dhcor-som",
"st,stm32mp135";
aliases {
ethernet0 = &ethernet1;
ethernet1 = &ethernet2;
serial2 = &usart1;
serial3 = &usart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&adc_1 {
pinctrl-names = "default";
pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>;
vdda-supply = <&vdd_adc>;
vref-supply = <&vdd_adc>;
status = "okay";
adc1: adc@0 {
status = "okay";
/*
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
* 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
* Use arbitrary margin here (e.g. 5us).
*
* The pinmux pins must be set as ANALOG, use datasheet
* DS13483 Table 7. STM32MP135C/F ball definitions to
* find out which 'pin name' maps to which 'additional
* functions', which lists the mapping between pin and
* ADC channel. In this case, PA5 maps to ADC1_INP2 and
* PF13 maps to ADC1_INP11 .
*/
channel@2 {
reg = <2>;
st,min-sample-time-ns = <5000>;
};
channel@11 {
reg = <11>;
st,min-sample-time-ns = <5000>;
};
/* Expansion connector: INP12:pin29 */
channel@12 {
reg = <12>;
st,min-sample-time-ns = <5000>;
};
};
};
&ethernet1 {
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
pinctrl-0 = <&eth1_rgmii_pins_a>;
pinctrl-1 = <&eth1_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
st,ext-phyclk;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
ethphy1: ethernet-phy@1 {
/* RTL8211F */
compatible = "ethernet-phy-id001c.c916";
interrupt-parent = <&gpiog>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
reg = <1>;
reset-assert-us = <15000>;
reset-deassert-us = <55000>;
reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
};
};
};
&ethernet2 {
phy-handle = <&ethphy2>;
phy-mode = "rgmii-id";
pinctrl-0 = <&eth2_rgmii_pins_a>;
pinctrl-1 = <&eth2_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
st,ext-phyclk;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
ethphy2: ethernet-phy@1 {
/* RTL8211F */
compatible = "ethernet-phy-id001c.c916";
interrupt-parent = <&gpiog>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
reg = <1>;
reset-assert-us = <15000>;
reset-deassert-us = <55000>;
reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>;
};
};
};
&gpioa {
gpio-line-names = "", "", "", "",
"", "DHSBC_USB_PWR_CC1", "", "",
"", "", "", "DHSBC_nETH1_RST",
"", "DHCOR_HW-CODING_0", "", "";
};
&gpiob {
gpio-line-names = "", "", "", "",
"", "", "", "DHCOR_BT_HOST_WAKE",
"", "", "", "",
"", "DHSBC_nTPM_CS", "", "";
};
&gpioc {
gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpiod {
gpio-line-names = "", "", "", "",
"", "DHCOR_RAM-CODING_0", "", "",
"", "DHCOR_RAM-CODING_1", "", "",
"", "", "", "";
};
&gpioe {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "DHSBC_nTPM_RST", "", "",
"DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", "";
};
&gpiof {
gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "",
"", "", "", "",
"", "", "", "",
"DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", "";
};
&gpiog {
gpio-line-names = "", "", "", "",
"", "", "", "",
"DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "",
"DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB";
};
&gpioi {
gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1",
"DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT",
"DHSBC_BOOT0", "DHSBC_BOOT1",
"DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS";
};
&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-1 = <&i2c1_sleep_pins_a>;
i2c-scl-rising-time-ns = <96>;
i2c-scl-falling-time-ns = <3>;
clock-frequency = <400000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_pins_b>;
pinctrl-1 = <&i2c5_sleep_pins_b>;
i2c-scl-rising-time-ns = <96>;
i2c-scl-falling-time-ns = <3>;
clock-frequency = <400000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can1_pins_a>;
pinctrl-1 = <&m_can1_sleep_pins_a>;
status = "okay";
};
&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can2_pins_a>;
pinctrl-1 = <&m_can2_sleep_pins_a>;
status = "okay";
};
&pwr_regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
status = "okay";
};
&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */
clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "x8k", "x11k";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>;
pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>;
};
&scmi_voltd {
status = "disabled";
};
&spi2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi2_pins_a>;
pinctrl-1 = <&spi2_sleep_pins_a>;
cs-gpios = <&gpiob 13 0>;
status = "okay";
st33htph: tpm@0 {
compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <24000000>;
};
};
&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi3_pins_a>;
pinctrl-1 = <&spi3_sleep_pins_a>;
cs-gpios = <&gpiof 3 0>;
status = "disabled";
};
&timers5 { /* Expansion connector: CH3:pin31 */
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
pwm {
pinctrl-0 = <&pwm5_pins_a>;
pinctrl-1 = <&pwm5_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@4 {
status = "okay";
};
};
&timers13 { /* Expansion connector: CH1:pin32 */
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
pwm {
pinctrl-0 = <&pwm13_pins_a>;
pinctrl-1 = <&pwm13_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@12 {
status = "okay";
};
};
&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart1_pins_b>;
pinctrl-1 = <&usart1_sleep_pins_b>;
pinctrl-2 = <&usart1_idle_pins_b>;
status = "okay";
};
&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart2_pins_b>;
pinctrl-1 = <&usart2_sleep_pins_b>;
pinctrl-2 = <&usart2_idle_pins_b>;
uart-has-rtscts;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbh_ohci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
dr_mode = "peripheral";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
usb33d-supply = <&usb33>;
status = "okay";
};
&usbphyc {
status = "okay";
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
st,current-boost-microamp = <1000>;
st,decrease-hs-slew-rate;
st,tune-hs-dc-level = <2>;
st,enable-hs-rftime-reduction;
st,trim-hs-current = <11>;
st,trim-hs-impedance = <2>;
st,tune-squelch-level = <1>;
st,enable-hs-rx-gain-eq;
st,no-hs-ftime-ctrl;
st,no-lsfs-sc;
connector {
compatible = "usb-a-connector";
vbus-supply = <&vbus_sw>;
};
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
st,current-boost-microamp = <1000>;
st,decrease-hs-slew-rate;
st,tune-hs-dc-level = <2>;
st,enable-hs-rftime-reduction;
st,trim-hs-current = <11>;
st,trim-hs-impedance = <2>;
st,tune-squelch-level = <1>;
st,enable-hs-rx-gain-eq;
st,no-hs-ftime-ctrl;
st,no-lsfs-sc;
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
label = "Type-C";
self-powered;
type = "micro";
};
};

128
arch/arm/boot/dts/st/stm32mp135f-dk.dts
View File

@@ -19,6 +19,7 @@
compatible = "st,stm32mp135f-dk", "st,stm32mp135";
aliases {
ethernet0 = &ethernet1;
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
@@ -29,6 +30,20 @@
stdout-path = "serial0:115200n8";
};
clocks {
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_mco1: clk-mco1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
@@ -141,6 +156,45 @@
status = "okay";
};
&dcmipp {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcmipp_pins_a>;
pinctrl-1 = <&dcmipp_sleep_pins_a>;
status = "okay";
port {
dcmipp_0: endpoint {
remote-endpoint = <&mipid02_2>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <0>;
};
};
};
&ethernet1 {
status = "okay";
pinctrl-0 = <&eth1_rmii_pins_a>;
pinctrl-1 = <&eth1_rmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
phy-handle = <&phy0_eth1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0_eth1: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.c131";
reg = <0>;
reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
@@ -201,6 +255,76 @@
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
stmipi: csi2rx@14 {
compatible = "st,st-mipid02";
reg = <0x14>;
clocks = <&clk_mco1>;
clock-names = "xclk";
VDDE-supply = <&scmi_v1v8_periph>;
VDDIN-supply = <&scmi_v1v8_periph>;
reset-gpios = <&mcp23017 2 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mipid02_0: endpoint {
data-lanes = <1 2>;
lane-polarities = <0 0 0>;
remote-endpoint = <&gc2145_ep>;
};
};
port@2 {
reg = <2>;
mipid02_2: endpoint {
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <0>;
remote-endpoint = <&dcmipp_0>;
};
};
};
};
gc2145: camera@3c {
compatible = "galaxycore,gc2145";
reg = <0x3c>;
clocks = <&clk_ext_camera>;
iovdd-supply = <&scmi_v3v3_sw>;
avdd-supply = <&scmi_v3v3_sw>;
dvdd-supply = <&scmi_v3v3_sw>;
powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
status = "okay";
port {
gc2145_ep: endpoint {
remote-endpoint = <&mipid02_0>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <120000000 192000000 240000000>;
};
};
};
goodix: goodix-ts@5d {
compatible = "goodix,gt911";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&goodix_pins_a>;
interrupt-parent = <&gpiof>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
AVDD28-supply = <&scmi_v3v3_sw>;
VDDIO-supply = <&scmi_v3v3_sw>;
touchscreen-size-x = <480>;
touchscreen-size-y = <272>;
status = "okay" ;
};
};
&iwdg2 {
@@ -273,6 +397,7 @@
/delete-property/dma-names;
status = "disabled";
pwm {
/* PWM output on pin 7 of the expansion connector (CN8.7) using TIM3_CH4 func */
pinctrl-0 = <&pwm3_pins_a>;
pinctrl-1 = <&pwm3_sleep_pins_a>;
pinctrl-names = "default", "sleep";
@@ -288,6 +413,7 @@
/delete-property/dma-names;
status = "disabled";
pwm {
/* PWM output on pin 31 of the expansion connector (CN8.31) using TIM4_CH2 func */
pinctrl-0 = <&pwm4_pins_a>;
pinctrl-1 = <&pwm4_sleep_pins_a>;
pinctrl-names = "default", "sleep";
@@ -303,6 +429,7 @@
/delete-property/dma-names;
status = "disabled";
pwm {
/* PWM output on pin 32 of the expansion connector (CN8.32) using TIM8_CH3 func */
pinctrl-0 = <&pwm8_pins_a>;
pinctrl-1 = <&pwm8_sleep_pins_a>;
pinctrl-names = "default", "sleep";
@@ -316,6 +443,7 @@
&timers14 {
status = "disabled";
pwm {
/* PWM output on pin 33 of the expansion connector (CN8.33) using TIM14_CH1 func */
pinctrl-0 = <&pwm14_pins_a>;
pinctrl-1 = <&pwm14_sleep_pins_a>;
pinctrl-names = "default", "sleep";

308
arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi Normal file
View File

@@ -0,0 +1,308 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2024 Marek Vasut <marex@denx.de>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mfd/st,stpmic1.h>
#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
#include "stm32mp13-pinctrl.dtsi"
/ {
model = "DH electronics STM32MP13xx DHCOR SoM";
compatible = "dh,stm32mp131a-dhcor-som",
"st,stm32mp131";
aliases {
mmc0 = &sdmmc2;
mmc1 = &sdmmc1;
serial0 = &uart4;
serial1 = &uart7;
rtc0 = &rv3032;
spi0 = &qspi;
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
optee@dd000000 {
reg = <0xdd000000 0x3000000>;
no-map;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>;
};
vin: vin {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&i2c3 {
i2c-scl-rising-time-ns = <96>;
i2c-scl-falling-time-ns = <3>;
clock-frequency = <400000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
regulators {
compatible = "st,stpmic1-regulators";
ldo1-supply = <&vin>;
ldo2-supply = <&vin>;
ldo3-supply = <&vin>;
ldo4-supply = <&vin>;
ldo5-supply = <&vin>;
ldo6-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
vddcpu: buck1 { /* VDD_CPU_1V2 */
regulator-name = "vddcpu";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd_ddr: buck2 { /* VDD_DDR_1V35 */
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd: buck3 { /* VDD_3V3_1V8 */
regulator-name = "vdd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vddcore: buck4 { /* VDD_CORE_1V2 */
regulator-name = "vddcore";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd_adc: ldo1 { /* VDD_ADC_1V8 */
regulator-name = "vdd_adc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO1 0>;
};
vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */
regulator-name = "vdd_ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO2 0>;
};
vdd_ldo3: ldo3 { /* LDO3_OUT */
regulator-name = "vdd_ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO3 0>;
};
vdd_usb: ldo4 { /* VDD_USB_3V3 */
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */
regulator-name = "vdd_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO5 0>;
};
vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */
regulator-name = "vdd_sd2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO6 0>;
};
vref_ddr: vref_ddr { /* VREF_DDR_0V675 */
regulator-name = "vref_ddr";
regulator-always-on;
};
bst_out: boost { /* BST_OUT_5V2 */
regulator-name = "bst_out";
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge = <1>;
};
};
onkey {
compatible = "st,stpmic1-onkey";
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
interrupt-names = "onkey-falling", "onkey-rising";
status = "okay";
};
watchdog {
compatible = "st,stpmic1-wdt";
status = "disabled";
};
};
eeprom0: eeprom@50 {
compatible = "atmel,24c256"; /* ST M24256 */
reg = <0x50>;
pagesize = <64>;
};
rv3032: rtc@51 {
compatible = "microcrystal,rv3032";
reg = <0x51>;
interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>;
};
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a
&qspi_bk1_pins_a
&qspi_cs1_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a
&qspi_bk1_sleep_pins_a
&qspi_cs1_sleep_pins_a>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
/* Console UART */
&uart4 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_b>;
pinctrl-1 = <&uart4_sleep_pins_b>;
pinctrl-2 = <&uart4_idle_pins_b>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
/* Bluetooth */
&uart7 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart7_pins_a>;
pinctrl-1 = <&uart7_sleep_pins_a>;
pinctrl-2 = <&uart7_idle_pins_a>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
max-speed = <3000000>;
device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
};
};
/* SDIO WiFi */
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
non-removable;
st,neg-edge;
vmmc-supply = <&vdd>;
mmc-pwrseq = <&sdio_pwrseq>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: bcrmf@1 { /* muRata 1YN */
reg = <1>;
compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
interrupt-parent = <&gpioe>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
/* eMMC */
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
bus-width = <8>;
mmc-ddr-3_3v;
no-sd;
no-sdio;
non-removable;
st,neg-edge;
vmmc-supply = <&vdd>;
vqmmc-supply = <&vdd>;
status = "okay";
};

1
arch/arm/boot/dts/st/stm32mp151.dtsi
View File

@@ -50,6 +50,7 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>;
arm,no-tick-in-suspend;
};
clocks {

5
arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
View File

@@ -62,6 +62,11 @@
reset-names = "mcu_rst", "hold_boot";
};
&optee {
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
&rcc {
compatible = "st,stm32mp1-rcc-secure", "syscon";
clock-names = "hse", "hsi", "csi", "lse", "lsi";

5
arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
View File

@@ -68,6 +68,11 @@
reset-names = "mcu_rst", "hold_boot";
};
&optee {
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
&rcc {
compatible = "st,stm32mp1-rcc-secure", "syscon";
clock-names = "hse", "hsi", "csi", "lse", "lsi";

5
arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
View File

@@ -67,6 +67,11 @@
reset-names = "mcu_rst", "hold_boot";
};
&optee {
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
&rcc {
compatible = "st,stm32mp1-rcc-secure", "syscon";
clock-names = "hse", "hsi", "csi", "lse", "lsi";

5
arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
View File

@@ -72,6 +72,11 @@
reset-names = "mcu_rst", "hold_boot";
};
&optee {
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
&rcc {
compatible = "st,stm32mp1-rcc-secure", "syscon";
clock-names = "hse", "hsi", "csi", "lse", "lsi";

13
arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts
View File

@@ -147,11 +147,6 @@
status = "okay";
};
&pwr_regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&rtc {
status = "okay";
};
@@ -211,11 +206,3 @@
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

13
arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi
View File

@@ -379,11 +379,6 @@ baseboard_eeprom: &sip_eeprom {
};
};
&pwr_regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&rtc {
status = "okay";
};
@@ -590,14 +585,6 @@ baseboard_eeprom: &sip_eeprom {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};
&vrefbuf {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;

13
arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi
View File

@@ -214,3 +214,16 @@
&rng1 {
status = "okay";
};
&pwr_regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

100
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
View File

@@ -6,6 +6,65 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
eth2_rgmii_pins_a: eth2-rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('C', 8, AF10)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 9, AF10)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('C', 10, AF10)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('C', 4, AF10)>; /* ETH_RGMII_TX_CTL */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('F', 7, AF10)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('C', 6, AF10)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins3 {
pinmux = <STM32_PINMUX('C', 5, AF10)>; /* ETH_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins4 {
pinmux = <STM32_PINMUX('G', 0, AF10)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 12, AF10)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('F', 9, AF10)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */
bias-disable;
};
pins5 {
pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */
bias-disable;
};
};
eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('C', 8, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 9, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('C', 10, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('F', 8, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('C', 6, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('G', 0, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 12, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('F', 9, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('C', 11, ANALOG)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('C', 3, ANALOG)>, /* ETH_RGMII_RX_CTL */
<STM32_PINMUX('F', 6, ANALOG)>; /* ETH_RGMII_RX_CLK */
};
};
i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, AF9)>, /* I2C2_SCL */
@@ -128,6 +187,47 @@
<STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
};
};
usart6_pins_a: usart6-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 13, AF3)>, /* USART6_TX */
<STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 14, AF3)>, /* USART6_RX */
<STM32_PINMUX('F', 15, AF3)>; /* USART6_CTS_NSS */
bias-pull-up;
};
};
usart6_idle_pins_a: usart6-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
<STM32_PINMUX('F', 15, ANALOG)>; /* USART6_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('F', 14, AF3)>; /* USART6_RX */
bias-pull-up;
};
};
usart6_sleep_pins_a: usart6-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
<STM32_PINMUX('G', 5, ANALOG)>, /* USART6_RTS */
<STM32_PINMUX('F', 15, ANALOG)>, /* USART6_CTS_NSS */
<STM32_PINMUX('F', 14, ANALOG)>; /* USART6_RX */
};
};
};
&pinctrl_z {

246
arch/arm64/boot/dts/st/stm32mp251.dtsi
View File

@@ -6,6 +6,7 @@
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
#include <dt-bindings/regulator/st,stm32mp25-regulator.h>
/ {
#address-cells = <2>;
@@ -20,6 +21,8 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
};
};
@@ -51,9 +54,11 @@
};
firmware {
optee {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
scmi {
@@ -71,6 +76,40 @@
reg = <0x16>;
#reset-cells = <1>;
};
scmi_voltd: protocol@17 {
reg = <0x17>;
scmi_regu: regulators {
#address-cells = <1>;
#size-cells = <0>;
scmi_vddio1: regulator@0 {
reg = <VOLTD_SCMI_VDDIO1>;
regulator-name = "vddio1";
};
scmi_vddio2: regulator@1 {
reg = <VOLTD_SCMI_VDDIO2>;
regulator-name = "vddio2";
};
scmi_vddio3: regulator@2 {
reg = <VOLTD_SCMI_VDDIO3>;
regulator-name = "vddio3";
};
scmi_vddio4: regulator@3 {
reg = <VOLTD_SCMI_VDDIO4>;
regulator-name = "vddio4";
};
scmi_vdd33ucpd: regulator@5 {
reg = <VOLTD_SCMI_UCPD>;
regulator-name = "vdd33ucpd";
};
scmi_vdda18adc: regulator@7 {
reg = <VOLTD_SCMI_ADC>;
regulator-name = "vdda18adc";
};
};
};
};
};
@@ -88,6 +127,20 @@
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CLUSTER_PD: power-domain-cluster {
#power-domain-cells = <0>;
power-domains = <&RET_PD>;
};
RET_PD: power-domain-retention {
#power-domain-cells = <0>;
};
};
timer {
@@ -107,6 +160,75 @@
interrupt-parent = <&intc>;
ranges = <0x0 0x0 0x0 0x80000000>;
hpdma: dma-controller@40400000 {
compatible = "st,stm32mp25-dma3";
reg = <0x40400000 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA1>;
#dma-cells = <3>;
};
hpdma2: dma-controller@40410000 {
compatible = "st,stm32mp25-dma3";
reg = <0x40410000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA2>;
#dma-cells = <3>;
};
hpdma3: dma-controller@40420000 {
compatible = "st,stm32mp25-dma3";
reg = <0x40420000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA3>;
#dma-cells = <3>;
};
rifsc: bus@42080000 {
compatible = "st,stm32mp25-rifsc", "simple-bus";
reg = <0x42080000 0x1000>;
@@ -148,6 +270,33 @@
status = "disabled";
};
usart3: serial@400f0000 {
compatible = "st,stm32h7-uart";
reg = <0x400f0000 0x400>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_USART3>;
access-controllers = <&rifsc 33>;
status = "disabled";
};
uart4: serial@40100000 {
compatible = "st,stm32h7-uart";
reg = <0x40100000 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_UART4>;
access-controllers = <&rifsc 34>;
status = "disabled";
};
uart5: serial@40110000 {
compatible = "st,stm32h7-uart";
reg = <0x40110000 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_UART5>;
access-controllers = <&rifsc 35>;
status = "disabled";
};
i2c1: i2c@40120000 {
compatible = "st,stm32mp25-i2c";
reg = <0x40120000 0x400>;
@@ -239,6 +388,15 @@
status = "disabled";
};
usart6: serial@40220000 {
compatible = "st,stm32h7-uart";
reg = <0x40220000 0x400>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_USART6>;
access-controllers = <&rifsc 36>;
status = "disabled";
};
spi1: spi@40230000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -275,6 +433,24 @@
status = "disabled";
};
uart9: serial@402c0000 {
compatible = "st,stm32h7-uart";
reg = <0x402c0000 0x400>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_UART9>;
access-controllers = <&rifsc 39>;
status = "disabled";
};
usart1: serial@40330000 {
compatible = "st,stm32h7-uart";
reg = <0x40330000 0x400>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_USART1>;
access-controllers = <&rifsc 31>;
status = "disabled";
};
spi6: spi@40350000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -299,6 +475,24 @@
status = "disabled";
};
uart7: serial@40370000 {
compatible = "st,stm32h7-uart";
reg = <0x40370000 0x400>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_UART7>;
access-controllers = <&rifsc 37>;
status = "disabled";
};
uart8: serial@40380000 {
compatible = "st,stm32h7-uart";
reg = <0x40380000 0x400>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_UART8>;
access-controllers = <&rifsc 38>;
status = "disabled";
};
spi8: spi@46020000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -338,6 +532,55 @@
access-controllers = <&rifsc 76>;
status = "disabled";
};
ethernet1: ethernet@482c0000 {
compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
reg = <0x482c0000 0x4000>;
reg-names = "stmmaceth";
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
"ptp_ref",
"ethstp",
"eth-ck";
clocks = <&rcc CK_ETH1_MAC>,
<&rcc CK_ETH1_TX>,
<&rcc CK_ETH1_RX>,
<&rcc CK_KER_ETH1PTP>,
<&rcc CK_ETH1_STP>,
<&rcc CK_KER_ETH1>;
snps,axi-config = <&stmmac_axi_config_1>;
snps,mixed-burst;
snps,mtl-rx-config = <&mtl_rx_setup_1>;
snps,mtl-tx-config = <&mtl_tx_setup_1>;
snps,pbl = <2>;
snps,tso;
st,syscon = <&syscfg 0x3000>;
access-controllers = <&rifsc 60>;
status = "disabled";
mtl_rx_setup_1: rx-queues-config {
snps,rx-queues-to-use = <2>;
queue0 {};
queue1 {};
};
mtl_tx_setup_1: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {};
queue1 {};
queue2 {};
queue3 {};
};
stmmac_axi_config_1: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <0x7>;
snps,wr_osr_lmt = <0x7>;
};
};
};
bsec: efuse@44000000 {
@@ -441,6 +684,7 @@
<&scmi_clk CK_SCMI_TIMG2>,
<&scmi_clk CK_SCMI_PLL3>,
<&clk_dsi_txbyte>;
access-controllers = <&rifsc 156>;
};
exti1: interrupt-controller@44220000 {

64
arch/arm64/boot/dts/st/stm32mp253.dtsi
View File

@@ -12,6 +12,8 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
};
};
@@ -21,6 +23,13 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
psci {
CPU_PD1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
};
timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
@@ -28,3 +37,58 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&optee {
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
&rifsc {
ethernet2: ethernet@482d0000 {
compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
reg = <0x482d0000 0x4000>;
reg-names = "stmmaceth";
interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
"ptp_ref",
"ethstp",
"eth-ck";
clocks = <&rcc CK_ETH2_MAC>,
<&rcc CK_ETH2_TX>,
<&rcc CK_ETH2_RX>,
<&rcc CK_KER_ETH2PTP>,
<&rcc CK_ETH2_STP>,
<&rcc CK_KER_ETH2>;
snps,axi-config = <&stmmac_axi_config_2>;
snps,mixed-burst;
snps,mtl-rx-config = <&mtl_rx_setup_2>;
snps,mtl-tx-config = <&mtl_tx_setup_2>;
snps,pbl = <2>;
snps,tso;
st,syscon = <&syscfg 0x3400>;
access-controllers = <&rifsc 61>;
status = "disabled";
mtl_rx_setup_2: rx-queues-config {
snps,rx-queues-to-use = <2>;
queue0 {};
queue1 {};
};
mtl_tx_setup_2: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {};
queue1 {};
queue2 {};
queue3 {};
};
stmmac_axi_config_2: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <0x7>;
snps,wr_osr_lmt = <0x7>;
};
};
};

77
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
View File

@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/st,stm32mp25-regulator.h>
#include "stm32mp257.dtsi"
#include "stm32mp25xf.dtsi"
#include "stm32mp25-pinctrl.dtsi"
@@ -17,7 +18,9 @@
compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
aliases {
ethernet0 = &ethernet2;
serial0 = &usart2;
serial1 = &usart6;
};
chosen {
@@ -40,14 +43,6 @@
no-map;
};
};
vdd_sdcard: vdd-sdcard {
compatible = "regulator-fixed";
regulator-name = "vdd_sdcard";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&arm_wdt {
@@ -55,6 +50,29 @@
status = "okay";
};
&ethernet2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth2_rgmii_pins_a>;
pinctrl-1 = <&eth2_rgmii_sleep_pins_a>;
max-speed = <1000>;
phy-handle = <&phy0_eth2>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0_eth2: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <1>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
reset-gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
};
};
};
&i2c2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_pins_a>;
@@ -75,6 +93,37 @@
status = "disabled";
};
&scmi_regu {
scmi_vddio1: regulator@0 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
scmi_vddcore: regulator@11 {
reg = <VOLTD_SCMI_STPMIC2_BUCK2>;
regulator-name = "vddcore";
};
scmi_v1v8: regulator@14 {
reg = <VOLTD_SCMI_STPMIC2_BUCK5>;
regulator-name = "v1v8";
};
scmi_v3v3: regulator@16 {
reg = <VOLTD_SCMI_STPMIC2_BUCK7>;
regulator-name = "v3v3";
};
scmi_vdd_emmc: regulator@18 {
reg = <VOLTD_SCMI_STPMIC2_LDO2>;
regulator-name = "vdd_emmc";
};
scmi_vdd3v3_usb: regulator@20 {
reg = <VOLTD_SCMI_STPMIC2_LDO4>;
regulator-name = "vdd3v3_usb";
};
scmi_vdd_sdcard: regulator@23 {
reg = <VOLTD_SCMI_STPMIC2_LDO7>;
regulator-name = "vdd_sdcard";
};
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
@@ -84,7 +133,8 @@
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&vdd_sdcard>;
vmmc-supply = <&scmi_vdd_sdcard>;
vqmmc-supply = <&scmi_vddio1>;
status = "okay";
};
@@ -109,3 +159,12 @@
pinctrl-2 = <&usart2_sleep_pins_a>;
status = "okay";
};
&usart6 {
pinctrl-names = "default", "idle", "sleep";
pinctrl-0 = <&usart6_pins_a>;
pinctrl-1 = <&usart6_idle_pins_a>;
pinctrl-2 = <&usart6_sleep_pins_a>;
uart-has-rtscts;
status = "disabled";
};

48
include/dt-bindings/regulator/st,stm32mp25-regulator.h Normal file
View File

@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2024, STMicroelectronics - All Rights Reserved
*/
#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H
#define __DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H
/* SCMI voltage domains identifiers */
/* SOC Internal regulators */
#define VOLTD_SCMI_VDDIO1 0
#define VOLTD_SCMI_VDDIO2 1
#define VOLTD_SCMI_VDDIO3 2
#define VOLTD_SCMI_VDDIO4 3
#define VOLTD_SCMI_VDDIO 4
#define VOLTD_SCMI_UCPD 5
#define VOLTD_SCMI_USB33 6
#define VOLTD_SCMI_ADC 7
#define VOLTD_SCMI_GPU 8
#define VOLTD_SCMI_VREFBUF 9
/* STPMIC2 regulators */
#define VOLTD_SCMI_STPMIC2_BUCK1 10
#define VOLTD_SCMI_STPMIC2_BUCK2 11
#define VOLTD_SCMI_STPMIC2_BUCK3 12
#define VOLTD_SCMI_STPMIC2_BUCK4 13
#define VOLTD_SCMI_STPMIC2_BUCK5 14
#define VOLTD_SCMI_STPMIC2_BUCK6 15
#define VOLTD_SCMI_STPMIC2_BUCK7 16
#define VOLTD_SCMI_STPMIC2_LDO1 17
#define VOLTD_SCMI_STPMIC2_LDO2 18
#define VOLTD_SCMI_STPMIC2_LDO3 19
#define VOLTD_SCMI_STPMIC2_LDO4 20
#define VOLTD_SCMI_STPMIC2_LDO5 21
#define VOLTD_SCMI_STPMIC2_LDO6 22
#define VOLTD_SCMI_STPMIC2_LDO7 23
#define VOLTD_SCMI_STPMIC2_LDO8 24
#define VOLTD_SCMI_STPMIC2_REFDDR 25
/* External regulators */
#define VOLTD_SCMI_REGU0 26
#define VOLTD_SCMI_REGU1 27
#define VOLTD_SCMI_REGU2 28
#define VOLTD_SCMI_REGU3 29
#define VOLTD_SCMI_REGU4 30
#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H */