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To configure and enable the DSI PHY PLL clocks, the MDSS AHB clock must be active for MMIO operations. Typically, this AHB clock is enabled as part of the DSI PHY interface enabling (dsi_phy_enable_resource). However, since these PLL clocks are registered as clock entities, they can be enabled independently of the DSI PHY interface, leading to enabling failures and subsequent warnings: ``` msm_dsi_phy 5e94400.phy: [drm:dsi_pll_14nm_vco_prepare] *ERROR* DSI PLL lock failed ------------[ cut here ]------------ dsi0pllbyte already disabled WARNING: CPU: 3 PID: 1 at drivers/clk/clk.c:1194 clk_core_disable+0xa4/0xac CPU: 3 UID: 0 PID: 1 Comm: swapper/0 Tainted: Tainted: [W]=WARN Hardware name: Qualcomm Technologies, Inc. Robotics RB1 (DT) pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [...] ``` This issue is particularly prevalent at boot time during the disabling of unused clocks (clk_disable_unused()) which includes enabling the parent clock(s) when CLK_OPS_PARENT_ENABLE flag is set (this is the case for the 14nm DSI PHY PLL consumers). To resolve this issue, we move the AHB clock as a PM dependency of the DSI PHY device (via pm_clk). Since the DSI PHY device is the parent of the PLL clocks, this resolves the PLL/AHB dependency. Now the AHB clock is enabled prior the PLL clk_prepare callback, as part of the runtime-resume chain. We also eliminate dsi_phy_[enable|disable]_resource functions, which are superseded by runtime PM. Note that it breaks compatibility with kernels before 6.0, as we do not support anymore the legacy `iface_clk` name. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/663239/ Link: https://lore.kernel.org/r/20250709140836.124143-1-loic.poulain@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
140 lines
4.1 KiB
C
140 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DSI_PHY_H__
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#define __DSI_PHY_H__
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#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/regulator/consumer.h>
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#include "dsi.h"
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struct msm_dsi_phy_ops {
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int (*pll_init)(struct msm_dsi_phy *phy);
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int (*enable)(struct msm_dsi_phy *phy,
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struct msm_dsi_phy_clk_request *clk_req);
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void (*disable)(struct msm_dsi_phy *phy);
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void (*save_pll_state)(struct msm_dsi_phy *phy);
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int (*restore_pll_state)(struct msm_dsi_phy *phy);
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bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);
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int (*parse_dt_properties)(struct msm_dsi_phy *phy);
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};
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struct msm_dsi_phy_cfg {
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const struct regulator_bulk_data *regulator_data;
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int num_regulators;
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struct msm_dsi_phy_ops ops;
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unsigned long min_pll_rate;
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unsigned long max_pll_rate;
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const resource_size_t io_start[DSI_MAX];
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const int num_dsi_phy;
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const int quirks;
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bool has_phy_regulator;
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bool has_phy_lane;
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};
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs;
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struct msm_dsi_dphy_timing {
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u32 clk_zero;
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u32 clk_trail;
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u32 clk_prepare;
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u32 hs_exit;
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u32 hs_zero;
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u32 hs_prepare;
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u32 hs_trail;
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u32 hs_rqst;
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u32 ta_go;
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u32 ta_sure;
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u32 ta_get;
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struct msm_dsi_phy_shared_timings shared_timings;
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/* For PHY v2 only */
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u32 hs_rqst_ckln;
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u32 hs_prep_dly;
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u32 hs_prep_dly_ckln;
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u8 hs_halfbyte_en;
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u8 hs_halfbyte_en_ckln;
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};
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#define NUM_PROVIDED_CLKS (DSI_PIXEL_PLL_CLK + 1)
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#define DSI_LANE_MAX 5
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struct msm_dsi_phy {
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struct platform_device *pdev;
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void __iomem *base;
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void __iomem *pll_base;
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void __iomem *reg_base;
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void __iomem *lane_base;
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phys_addr_t base_size;
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phys_addr_t pll_size;
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phys_addr_t reg_size;
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phys_addr_t lane_size;
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int id;
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struct regulator_bulk_data *supplies;
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struct msm_dsi_dphy_timing timing;
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const struct msm_dsi_phy_cfg *cfg;
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void *tuning_cfg;
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enum msm_dsi_phy_usecase usecase;
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bool regulator_ldo_mode;
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bool cphy_mode;
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struct clk_hw *vco_hw;
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bool pll_on;
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struct clk_hw_onecell_data *provided_clocks;
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bool state_saved;
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};
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/*
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* PHY internal functions
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*/
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int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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#endif /* __DSI_PHY_H__ */
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