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8b549c18ae
This came up in the discussion of the requirements of qspinlock on an
architecture. OpenRISC uses qspinlock, but it was noticed that the
memmory barrier was not defined.
Peter defined it in the mail thread writing:
As near as I can tell this should do. The arch spec only lists
this one instruction and the text makes it sound like a completion
barrier.
This is correct so applying this patch.
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
[shorne@gmail.com:Turned the mail into a patch]
Signed-off-by: Stafford Horne <shorne@gmail.com>
10 lines
203 B
C
10 lines
203 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#define mb() asm volatile ("l.msync" ::: "memory")
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#include <asm-generic/barrier.h>
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#endif /* __ASM_BARRIER_H */
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