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f04660e48b
Add nodes for the SRAM available on atmel SoCs For the at91sam9260 and the at91sam9g20, address mirroring is used to create a single contiguous SRAM range instead of declaring two separate banks. Also remove leftover TODOs in the sam9g45 file Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> [nicolas.ferre@atmel.com: correct at91sam9rl sram size => 0x10000] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
69 lines
1.4 KiB
Plaintext
69 lines
1.4 KiB
Plaintext
/*
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* at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
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*
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* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* Licensed under GPLv2.
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*/
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#include "at91sam9260.dtsi"
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/ {
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model = "Atmel AT91SAM9G20 family SoC";
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compatible = "atmel,at91sam9g20";
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memory {
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reg = <0x20000000 0x08000000>;
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};
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sram0: sram@002ff000 {
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status = "disabled";
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};
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sram1: sram@002fc000 {
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compatible = "mmio-sram";
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reg = <0x002fc000 0x8000>;
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};
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ahb {
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apb {
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i2c0: i2c@fffac000 {
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compatible = "atmel,at91sam9g20-i2c";
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};
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ssc0: ssc@fffbc000 {
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compatible = "atmel,at91sam9rl-ssc";
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};
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adc0: adc@fffe0000 {
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atmel,adc-startup-time = <40>;
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};
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pmc: pmc@fffffc00 {
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plla: pllack {
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atmel,clk-input-range = <2000000 32000000>;
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atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
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<695000000 750000000 1 0>,
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<645000000 700000000 2 0>,
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<595000000 650000000 3 0>,
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<545000000 600000000 0 1>,
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<495000000 550000000 1 1>,
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<445000000 500000000 2 1>,
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<400000000 450000000 3 1>;
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};
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pllb: pllbck {
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compatible = "atmel,at91sam9g20-clk-pllb";
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atmel,clk-input-range = <2000000 32000000>;
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atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
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};
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mck: masterck {
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atmel,clk-output-range = <0 133000000>;
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atmel,clk-divisors = <1 2 4 6>;
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};
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};
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};
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};
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};
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