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f4acea9eef
STM32 SPI may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 SPI. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Link: https://patch.msgid.link/20251215-stm32-spi-mp2x-dt-updates-v1-1-464a5fd20f13@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
134 lines
3.0 KiB
YAML
134 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 SPI Controller
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description: |
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The STM32 SPI controller is used to communicate with external devices using
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the Serial Peripheral Interface. It supports full-duplex, half-duplex and
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simplex synchronous serial communication with external devices. It supports
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from 4 to 32-bit data size.
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maintainers:
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- Erwan Leray <erwan.leray@foss.st.com>
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- Fabrice Gasnier <fabrice.gasnier@foss.st.com>
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32f4-spi
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then:
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properties:
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st,spi-midi-ns: false
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sram: false
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: rx
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- const: tx
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32mp25-spi
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then:
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properties:
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sram: false
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: rx
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- const: tx
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properties:
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compatible:
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enum:
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- st,stm32f4-spi
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- st,stm32f7-spi
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- st,stm32h7-spi
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- st,stm32mp25-spi
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 1
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resets:
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maxItems: 1
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dmas:
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description: |
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DMA specifiers for tx and rx channels. DMA fifo mode must be used. See
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the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32/st,*dma.yaml
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minItems: 2
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items:
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- description: rx DMA channel
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- description: tx DMA channel
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- description: rxm2m MDMA channel
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dma-names:
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minItems: 2
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items:
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- const: rx
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- const: tx
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- const: rxm2m
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sram:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: |
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Phandles to a reserved SRAM region which is used as temporary
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storage memory between DMA and MDMA engines.
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The region should be defined as child node of the AHB SRAM node
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as per the generic bindings in Documentation/devicetree/bindings/sram/sram.yaml
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power-domains:
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maxItems: 1
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access-controllers:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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spi@4000b000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x4000b000 0x400>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc SPI2_K>;
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resets = <&rcc SPI2_R>;
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dmas = <&dmamux1 0 39 0x400 0x05>,
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<&dmamux1 1 40 0x400 0x05>;
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dma-names = "rx", "tx";
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cs-gpios = <&gpioa 11 0>;
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};
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...
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