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	 667d1b48bc
			
		
	
	
		667d1b48bc
		
	
	
	
	
		
			
			Fixup entries in the kernel exception tables should be 4-byte aligned since we return directly to them when handling a faulting instruction in the kernel. This patch adds the missing align directives to the fixup entries. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
		
			
				
	
	
		
			170 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			170 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| #ifndef _ASM_ARM_FUTEX_H
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| #define _ASM_ARM_FUTEX_H
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| 
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| #ifdef __KERNEL__
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| 
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| #if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP)
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| /* ARM doesn't provide unprivileged exclusive memory accessors */
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| #include <asm-generic/futex.h>
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| #else
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| 
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| #include <linux/futex.h>
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| #include <linux/uaccess.h>
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| #include <asm/errno.h>
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| 
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| #define __futex_atomic_ex_table(err_reg)			\
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| 	"3:\n"							\
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| 	"	.pushsection __ex_table,\"a\"\n"		\
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| 	"	.align	3\n"					\
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| 	"	.long	1b, 4f, 2b, 4f\n"			\
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| 	"	.popsection\n"					\
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| 	"	.pushsection .fixup,\"ax\"\n"			\
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| 	"	.align	2\n"					\
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| 	"4:	mov	%0, " err_reg "\n"			\
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| 	"	b	3b\n"					\
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| 	"	.popsection"
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| 
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| #ifdef CONFIG_SMP
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| 
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| #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg)	\
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| 	smp_mb();						\
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| 	__asm__ __volatile__(					\
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| 	"1:	ldrex	%1, [%3]\n"				\
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| 	"	" insn "\n"					\
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| 	"2:	strex	%2, %0, [%3]\n"				\
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| 	"	teq	%2, #0\n"				\
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| 	"	bne	1b\n"					\
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| 	"	mov	%0, #0\n"				\
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| 	__futex_atomic_ex_table("%5")				\
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| 	: "=&r" (ret), "=&r" (oldval), "=&r" (tmp)		\
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| 	: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT)		\
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| 	: "cc", "memory")
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| 
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| static inline int
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| futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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| 			      u32 oldval, u32 newval)
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| {
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| 	int ret;
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| 	u32 val;
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| 
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| 	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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| 		return -EFAULT;
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| 
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| 	smp_mb();
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| 	__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
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| 	"1:	ldrex	%1, [%4]\n"
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| 	"	teq	%1, %2\n"
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| 	"	ite	eq	@ explicit IT needed for the 2b label\n"
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| 	"2:	strexeq	%0, %3, [%4]\n"
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| 	"	movne	%0, #0\n"
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| 	"	teq	%0, #0\n"
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| 	"	bne	1b\n"
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| 	__futex_atomic_ex_table("%5")
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| 	: "=&r" (ret), "=&r" (val)
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| 	: "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
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| 	: "cc", "memory");
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| 	smp_mb();
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| 
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| 	*uval = val;
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| 	return ret;
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| }
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| 
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| #else /* !SMP, we can work around lack of atomic ops by disabling preemption */
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| 
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| #include <linux/preempt.h>
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| #include <asm/domain.h>
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| 
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| #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg)	\
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| 	__asm__ __volatile__(					\
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| 	"1:	" TUSER(ldr) "	%1, [%3]\n"			\
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| 	"	" insn "\n"					\
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| 	"2:	" TUSER(str) "	%0, [%3]\n"			\
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| 	"	mov	%0, #0\n"				\
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| 	__futex_atomic_ex_table("%5")				\
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| 	: "=&r" (ret), "=&r" (oldval), "=&r" (tmp)		\
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| 	: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT)		\
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| 	: "cc", "memory")
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| 
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| static inline int
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| futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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| 			      u32 oldval, u32 newval)
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| {
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| 	int ret = 0;
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| 	u32 val;
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| 
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| 	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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| 		return -EFAULT;
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| 
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| 	__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
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| 	"1:	" TUSER(ldr) "	%1, [%4]\n"
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| 	"	teq	%1, %2\n"
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| 	"	it	eq	@ explicit IT needed for the 2b label\n"
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| 	"2:	" TUSER(streq) "	%3, [%4]\n"
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| 	__futex_atomic_ex_table("%5")
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| 	: "+r" (ret), "=&r" (val)
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| 	: "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
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| 	: "cc", "memory");
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| 
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| 	*uval = val;
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| 	return ret;
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| }
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| 
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| #endif /* !SMP */
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| 
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| static inline int
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| futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
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| {
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| 	int op = (encoded_op >> 28) & 7;
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| 	int cmp = (encoded_op >> 24) & 15;
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| 	int oparg = (encoded_op << 8) >> 20;
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| 	int cmparg = (encoded_op << 20) >> 20;
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| 	int oldval = 0, ret, tmp;
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| 
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| 	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
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| 		oparg = 1 << oparg;
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| 
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| 	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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| 		return -EFAULT;
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| 
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| 	pagefault_disable();	/* implies preempt_disable() */
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| 
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| 	switch (op) {
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| 	case FUTEX_OP_SET:
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| 		__futex_atomic_op("mov	%0, %4", ret, oldval, tmp, uaddr, oparg);
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| 		break;
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| 	case FUTEX_OP_ADD:
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| 		__futex_atomic_op("add	%0, %1, %4", ret, oldval, tmp, uaddr, oparg);
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| 		break;
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| 	case FUTEX_OP_OR:
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| 		__futex_atomic_op("orr	%0, %1, %4", ret, oldval, tmp, uaddr, oparg);
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| 		break;
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| 	case FUTEX_OP_ANDN:
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| 		__futex_atomic_op("and	%0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
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| 		break;
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| 	case FUTEX_OP_XOR:
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| 		__futex_atomic_op("eor	%0, %1, %4", ret, oldval, tmp, uaddr, oparg);
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| 		break;
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| 	default:
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| 		ret = -ENOSYS;
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| 	}
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| 
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| 	pagefault_enable();	/* subsumes preempt_enable() */
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| 
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| 	if (!ret) {
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| 		switch (cmp) {
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| 		case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
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| 		case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
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| 		case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
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| 		case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
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| 		case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
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| 		case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
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| 		default: ret = -ENOSYS;
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| 		}
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| 	}
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| 	return ret;
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| }
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| 
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| #endif /* !(CPU_USE_DOMAINS && SMP) */
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| #endif /* __KERNEL__ */
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| #endif /* _ASM_ARM_FUTEX_H */
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