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d027db132b
This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJQyLCjAAoJEIwa5zzehBx3AdQP/R+L3+EQMjiEWt/p7g/ql5Em 0SnP92CcGzrjgLTg9z1FeOazfOsGnkZAYUlDRkqfKobH3VqkhYFFtt1/0x0KMahm xcowHgMBOyimFdWT9vLK3J8U6DLui5XrEG9LGH2VL+lqmfjIyP/OOF3mVc0/+pV9 WTLAsYswdBRSeiNuF43kqlfrOwF6xsPLgiNMlc82w6BzHqoHu6dOif5M9MqWaApS V74DPmwLD371Tyit6aHqt3JOqpgiPSHlmxkzomK+5idcW3Pa7HnzzFYmx85dk/eN J2siqIkoOu7tEfjIbNZTL2MYoX4tUUKv4qZZ3IOl3YSWaV3P5ilMApF01XVrkk8E DWOMhzte9hC7L90W+/kCPLF1VyeAhCem2KQWUitO71fKur3r+3ZaUokNVvWzkJIL 7aduxAJOV2hfLgEqbjbjF3o4S8p63OV3kzivFJM1And15zDJo4+qqOh67+bPo4jj +R4du+SqzXriw4i3tDLGVpdjDffk4D41tbLzgkWAtvGyoP45yeYfHAzAh0pDFPRv ASfZVmZ5PhwAUAkIMnpC2sjgmxMYff3SYqmDgnsqXES7rbDH/hG+teymtHFTyUQp m+f60DNotSMcMvkLdvruLSB4aeTiwbfOqPn/g+aXYUlPuNMq1fVWgN7EJKWkamK4 nRwaJmLwx1/ojcVbpy2G =YMKB -----END PGP SIGNATURE----- Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC updates from Olof Johansson: "This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms." Fix up trivial conflicts as per Olof. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits) mfd: vexpress-sysreg: Remove LEDs code irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids irq: versatile: delete dangling variable ARM: sunxi: add missing include for mdelay() ARM: EXYNOS: Avoid early use of of_machine_is_compatible() ARM: dts: add node for PL330 MDMA1 controller for exynos4 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412 ARM: EXYNOS: add UART3 to DEBUG_LL ports ARM: S3C24XX: Add clkdev entry for camif-upll clock ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers ARM: sunxi: Add missing sun4i.dtsi file pinctrl: samsung: Do not initialise statics to 0 ARM i.MX6: remove gate_mask from pllv3 ARM i.MX6: Fix ethernet PLL clocks ARM i.MX6: rename PLLs according to datasheet ARM i.MX6: Add pwm support ARM i.MX51: Add pwm support ARM i.MX53: Add pwm support ARM: mx5: Replace clk_register_clkdev with clock DT lookup ...
292 lines
9.1 KiB
C
292 lines
9.1 KiB
C
/* linux/arch/arm/mach-exynos/include/mach/map.h
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* EXYNOS4 - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H __FILE__
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#include <plat/map-base.h>
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/*
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* EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
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* So need to define it, and here is to avoid redefinition warning.
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*/
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#define S3C_UART_OFFSET (0x10000)
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#include <plat/map-s5p.h>
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#define EXYNOS4_PA_SYSRAM0 0x02025000
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#define EXYNOS4_PA_SYSRAM1 0x02020000
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#define EXYNOS5_PA_SYSRAM 0x02020000
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#define EXYNOS4_PA_FIMC0 0x11800000
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#define EXYNOS4_PA_FIMC1 0x11810000
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#define EXYNOS4_PA_FIMC2 0x11820000
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#define EXYNOS4_PA_FIMC3 0x11830000
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#define EXYNOS4_PA_JPEG 0x11840000
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/* x = 0...1 */
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#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
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#define EXYNOS4_PA_G2D 0x12800000
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#define EXYNOS4_PA_I2S0 0x03830000
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#define EXYNOS4_PA_I2S1 0xE3100000
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#define EXYNOS4_PA_I2S2 0xE2A00000
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#define EXYNOS4_PA_PCM0 0x03840000
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#define EXYNOS4_PA_PCM1 0x13980000
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#define EXYNOS4_PA_PCM2 0x13990000
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#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
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#define EXYNOS4_PA_ONENAND 0x0C000000
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#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
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#define EXYNOS_PA_CHIPID 0x10000000
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#define EXYNOS5440_PA_CHIPID 0x00160000
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#define EXYNOS4_PA_SYSCON 0x10010000
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#define EXYNOS5_PA_SYSCON 0x10050100
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#define EXYNOS4_PA_PMU 0x10020000
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#define EXYNOS5_PA_PMU 0x10040000
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#define EXYNOS4_PA_CMU 0x10030000
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#define EXYNOS5_PA_CMU 0x10010000
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#define EXYNOS4_PA_SYSTIMER 0x10050000
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#define EXYNOS5_PA_SYSTIMER 0x101C0000
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#define EXYNOS4_PA_WATCHDOG 0x10060000
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#define EXYNOS5_PA_WATCHDOG 0x101D0000
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#define EXYNOS4_PA_RTC 0x10070000
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#define EXYNOS4_PA_KEYPAD 0x100A0000
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#define EXYNOS4_PA_DMC0 0x10400000
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#define EXYNOS4_PA_DMC1 0x10410000
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#define EXYNOS4_PA_COMBINER 0x10440000
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#define EXYNOS5_PA_COMBINER 0x10440000
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#define EXYNOS4_PA_GIC_CPU 0x10480000
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#define EXYNOS4_PA_GIC_DIST 0x10490000
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#define EXYNOS5_PA_GIC_CPU 0x10482000
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#define EXYNOS5_PA_GIC_DIST 0x10481000
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#define EXYNOS4_PA_COREPERI 0x10500000
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#define EXYNOS4_PA_TWD 0x10500600
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#define EXYNOS4_PA_L2CC 0x10502000
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#define EXYNOS4_PA_MDMA0 0x10810000
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#define EXYNOS4_PA_MDMA1 0x12850000
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#define EXYNOS4_PA_S_MDMA1 0x12840000
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#define EXYNOS4_PA_PDMA0 0x12680000
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#define EXYNOS4_PA_PDMA1 0x12690000
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#define EXYNOS5_PA_MDMA0 0x10800000
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#define EXYNOS5_PA_MDMA1 0x11C10000
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#define EXYNOS5_PA_PDMA0 0x121A0000
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#define EXYNOS5_PA_PDMA1 0x121B0000
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#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
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#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
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#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
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#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
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#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
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#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
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#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
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#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
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#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
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#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
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#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
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#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
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#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
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#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
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#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
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#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
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#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
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#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
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#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
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#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
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#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
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#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
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#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
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#define EXYNOS5_PA_GSC0 0x13E00000
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#define EXYNOS5_PA_GSC1 0x13E10000
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#define EXYNOS5_PA_GSC2 0x13E20000
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#define EXYNOS5_PA_GSC3 0x13E30000
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#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
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#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
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#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
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#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
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#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
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#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
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#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
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#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
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#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
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#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
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#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
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#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
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#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
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#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
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#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
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#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
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#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
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#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
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#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
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#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
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#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
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#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
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#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
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#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
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#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
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#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
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#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
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#define EXYNOS5_PA_SYSMMU_TV 0x14650000
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#define EXYNOS4_PA_SPI0 0x13920000
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#define EXYNOS4_PA_SPI1 0x13930000
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#define EXYNOS4_PA_SPI2 0x13940000
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#define EXYNOS5_PA_SPI0 0x12D20000
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#define EXYNOS5_PA_SPI1 0x12D30000
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#define EXYNOS5_PA_SPI2 0x12D40000
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#define EXYNOS4_PA_GPIO1 0x11400000
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#define EXYNOS4_PA_GPIO2 0x11000000
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#define EXYNOS4_PA_GPIO3 0x03860000
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#define EXYNOS5_PA_GPIO1 0x11400000
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#define EXYNOS5_PA_GPIO2 0x13400000
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#define EXYNOS5_PA_GPIO3 0x10D10000
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#define EXYNOS5_PA_GPIO4 0x03860000
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#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
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#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
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#define EXYNOS4_PA_FIMD0 0x11C00000
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#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
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#define EXYNOS4_PA_DWMCI 0x12550000
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#define EXYNOS5_PA_DWMCI0 0x12200000
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#define EXYNOS5_PA_DWMCI1 0x12210000
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#define EXYNOS5_PA_DWMCI2 0x12220000
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#define EXYNOS5_PA_DWMCI3 0x12230000
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#define EXYNOS4_PA_HSOTG 0x12480000
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#define EXYNOS4_PA_USB_HSPHY 0x125B0000
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#define EXYNOS4_PA_SATA 0x12560000
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#define EXYNOS4_PA_SATAPHY 0x125D0000
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#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
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#define EXYNOS4_PA_SROMC 0x12570000
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#define EXYNOS5_PA_SROMC 0x12250000
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#define EXYNOS4_PA_EHCI 0x12580000
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#define EXYNOS4_PA_OHCI 0x12590000
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#define EXYNOS4_PA_HSPHY 0x125B0000
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#define EXYNOS4_PA_MFC 0x13400000
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#define EXYNOS4_PA_UART 0x13800000
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#define EXYNOS5_PA_UART 0x12C00000
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#define EXYNOS4_PA_VP 0x12C00000
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#define EXYNOS4_PA_MIXER 0x12C10000
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#define EXYNOS4_PA_SDO 0x12C20000
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#define EXYNOS4_PA_HDMI 0x12D00000
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#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
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#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
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#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
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#define EXYNOS4_PA_ADC 0x13910000
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#define EXYNOS4_PA_ADC1 0x13911000
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#define EXYNOS4_PA_AC97 0x139A0000
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#define EXYNOS4_PA_SPDIF 0x139B0000
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#define EXYNOS4_PA_TIMER 0x139D0000
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#define EXYNOS5_PA_TIMER 0x12DD0000
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#define EXYNOS4_PA_SDRAM 0x40000000
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#define EXYNOS5_PA_SDRAM 0x40000000
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/* Compatibiltiy Defines */
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#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
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#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
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#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
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#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
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#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
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#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
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#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
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#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
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#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
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#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
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#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
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#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
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#define S3C_PA_RTC EXYNOS4_PA_RTC
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#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
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#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
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#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
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#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
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#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
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#define S5P_PA_EHCI EXYNOS4_PA_EHCI
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#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
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#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
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#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
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#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
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#define S5P_PA_JPEG EXYNOS4_PA_JPEG
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#define S5P_PA_G2D EXYNOS4_PA_G2D
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#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
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#define S5P_PA_HDMI EXYNOS4_PA_HDMI
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#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
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#define S5P_PA_MFC EXYNOS4_PA_MFC
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#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
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#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
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#define S5P_PA_MIXER EXYNOS4_PA_MIXER
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#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
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#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
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#define S5P_PA_SDO EXYNOS4_PA_SDO
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#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
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#define S5P_PA_VP EXYNOS4_PA_VP
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#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
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#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
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#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
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/* Compatibility UART */
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#define EXYNOS4_PA_UART0 0x13800000
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#define EXYNOS4_PA_UART1 0x13810000
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#define EXYNOS4_PA_UART2 0x13820000
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#define EXYNOS4_PA_UART3 0x13830000
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#define EXYNOS4_SZ_UART SZ_256
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#define EXYNOS5_PA_UART0 0x12C00000
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#define EXYNOS5_PA_UART1 0x12C10000
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#define EXYNOS5_PA_UART2 0x12C20000
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#define EXYNOS5_PA_UART3 0x12C30000
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#define EXYNOS5440_PA_UART0 0x000B0000
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#define EXYNOS5440_PA_UART1 0x000C0000
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#define EXYNOS5440_SZ_UART SZ_256
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#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
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#endif /* __ASM_ARCH_MAP_H */
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