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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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e0e0c87c02
This patch set contains a handful of fixes that clean up the sparse results for the RISC-V port. These patches shouldn't have any functional difference. The patches: * Use NULL instead of 0. * Clean up __user annotations. * Split __copy_user into two functions, to make the __user annotations valid. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
125 lines
2.2 KiB
ArmAsm
125 lines
2.2 KiB
ArmAsm
#include <linux/linkage.h>
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#include <asm/asm.h>
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#include <asm/csr.h>
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.altmacro
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.macro fixup op reg addr lbl
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LOCAL _epc
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_epc:
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\op \reg, \addr
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.section __ex_table,"a"
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.balign RISCV_SZPTR
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RISCV_PTR _epc, \lbl
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.previous
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.endm
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ENTRY(__asm_copy_to_user)
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ENTRY(__asm_copy_from_user)
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/* Enable access to user memory */
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li t6, SR_SUM
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csrs sstatus, t6
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add a3, a1, a2
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/* Use word-oriented copy only if low-order bits match */
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andi t0, a0, SZREG-1
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andi t1, a1, SZREG-1
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bne t0, t1, 2f
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addi t0, a1, SZREG-1
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andi t1, a3, ~(SZREG-1)
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andi t0, t0, ~(SZREG-1)
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/*
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* a3: terminal address of source region
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* t0: lowest XLEN-aligned address in source
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* t1: highest XLEN-aligned address in source
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*/
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bgeu t0, t1, 2f
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bltu a1, t0, 4f
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1:
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fixup REG_L, t2, (a1), 10f
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fixup REG_S, t2, (a0), 10f
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addi a1, a1, SZREG
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addi a0, a0, SZREG
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bltu a1, t1, 1b
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2:
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bltu a1, a3, 5f
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3:
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/* Disable access to user memory */
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csrc sstatus, t6
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li a0, 0
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ret
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4: /* Edge case: unalignment */
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fixup lbu, t2, (a1), 10f
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fixup sb, t2, (a0), 10f
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addi a1, a1, 1
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addi a0, a0, 1
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bltu a1, t0, 4b
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j 1b
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5: /* Edge case: remainder */
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fixup lbu, t2, (a1), 10f
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fixup sb, t2, (a0), 10f
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addi a1, a1, 1
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addi a0, a0, 1
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bltu a1, a3, 5b
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j 3b
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ENDPROC(__asm_copy_to_user)
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ENDPROC(__asm_copy_from_user)
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ENTRY(__clear_user)
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/* Enable access to user memory */
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li t6, SR_SUM
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csrs sstatus, t6
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add a3, a0, a1
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addi t0, a0, SZREG-1
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andi t1, a3, ~(SZREG-1)
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andi t0, t0, ~(SZREG-1)
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/*
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* a3: terminal address of target region
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* t0: lowest doubleword-aligned address in target region
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* t1: highest doubleword-aligned address in target region
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*/
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bgeu t0, t1, 2f
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bltu a0, t0, 4f
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1:
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fixup REG_S, zero, (a0), 11f
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addi a0, a0, SZREG
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bltu a0, t1, 1b
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2:
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bltu a0, a3, 5f
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3:
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/* Disable access to user memory */
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csrc sstatus, t6
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li a0, 0
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ret
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4: /* Edge case: unalignment */
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fixup sb, zero, (a0), 11f
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addi a0, a0, 1
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bltu a0, t0, 4b
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j 1b
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5: /* Edge case: remainder */
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fixup sb, zero, (a0), 11f
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addi a0, a0, 1
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bltu a0, a3, 5b
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j 3b
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ENDPROC(__clear_user)
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.section .fixup,"ax"
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.balign 4
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/* Fixup code for __copy_user(10) and __clear_user(11) */
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10:
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/* Disable access to user memory */
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csrs sstatus, t6
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mv a0, a2
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ret
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11:
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csrs sstatus, t6
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mv a0, a1
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ret
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.previous
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