mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-04 20:19:47 +08:00
cycle:
Core changes:
- Device links can optionally be added between a pin control
producer and its consumers. This will affect how the system
power management is handled: a pin controller will not suspend
before all of its consumers have been suspended. This was
necessary for the ST Microelectronics STMFX expander and
need to be tested on other systems as well: it makes sense
to make this default in the long run. Right now it is
opt-in per driver.
- Drive strength can be specified in microamps. With decreases
in silicon technology, milliamps isn't granular enough, let's
make it possible to select drive strengths in microamps. Right
now the Meson (AMlogic) driver needs this.
New drivers:
- New subdriver for the Tegra 194 SoC.
- New subdriver for the Qualcomm SDM845.
- New subdriver for the Qualcomm SM8150.
- New subdriver for the Freescale i.MX8MN (Freescale is now a
product line of NXP).
- New subdriver for Marvell MV98DX1135.
Driver improvements:
- The Bitmain BM1880 driver now supports pin config in
addition to muxing.
- The Qualcomm drivers can now reserve some GPIOs as taken
aside and not usable for users. This is used in ACPI systems
to take out some GPIO lines used by the BIOS so that
noone else (neither kernel nor userspace) will play with them
by mistake and crash the machine.
- A slew of refurbishing around the Aspeed drivers (board
management controllers for servers) in preparation for the
new Aspeed AST2600 SoC.
- A slew of improvements over the SH PFC drivers as usual.
- Misc cleanups and fixes.
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Merge tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.3 kernel cycle:
Core changes:
- Device links can optionally be added between a pin control producer
and its consumers. This will affect how the system power management
is handled: a pin controller will not suspend before all of its
consumers have been suspended.
This was necessary for the ST Microelectronics STMFX expander and
need to be tested on other systems as well: it makes sense to make
this default in the long run.
Right now it is opt-in per driver.
- Drive strength can be specified in microamps. With decreases in
silicon technology, milliamps isn't granular enough, let's make it
possible to select drive strengths in microamps.
Right now the Meson (AMlogic) driver needs this.
New drivers:
- New subdriver for the Tegra 194 SoC.
- New subdriver for the Qualcomm SDM845.
- New subdriver for the Qualcomm SM8150.
- New subdriver for the Freescale i.MX8MN (Freescale is now a product
line of NXP).
- New subdriver for Marvell MV98DX1135.
Driver improvements:
- The Bitmain BM1880 driver now supports pin config in addition to
muxing.
- The Qualcomm drivers can now reserve some GPIOs as taken aside and
not usable for users. This is used in ACPI systems to take out some
GPIO lines used by the BIOS so that noone else (neither kernel nor
userspace) will play with them by mistake and crash the machine.
- A slew of refurbishing around the Aspeed drivers (board management
controllers for servers) in preparation for the new Aspeed AST2600
SoC.
- A slew of improvements over the SH PFC drivers as usual.
- Misc cleanups and fixes"
* tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits)
pinctrl: aspeed: Strip moved macros and structs from private header
pinctrl: aspeed: Fix missed include
pinctrl: baytrail: Use GENMASK() consistently
pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
pinctrl: qcom: Add SM8150 pinctrl driver
dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
dt-bindings: pinctrl: qcom: Document missing gpio nodes
pinctrl: aspeed: Add implementation-related documentation
pinctrl: aspeed: Split out pinmux from general pinctrl
pinctrl: aspeed: Clarify comment about strapping W1C
pinctrl: aspeed: Correct comment that is no longer true
MAINTAINERS: Add entry for ASPEED pinctrl drivers
dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema
dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema
dt-bindings: pinctrl: aspeed: Split bindings document in two
pinctrl: qcom: Add irq_enable callback for msm gpio
pinctrl: madera: Fixup SPDX headers
pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard
pinctrl: tegra: Add bitmask support for parked bits
...
174 lines
4.2 KiB
C
174 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Pin controller and GPIO driver for Amlogic Meson SoCs
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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*/
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#include <linux/gpio/driver.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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/**
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* struct meson_pmx_group - a pinmux group
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*
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* @name: group name
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* @pins: pins in the group
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* @num_pins: number of pins in the group
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* @is_gpio: whether the group is a single GPIO group
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* @reg: register offset for the group in the domain mux registers
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* @bit bit index enabling the group
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* @domain: index of the domain this group belongs to
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*/
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struct meson_pmx_group {
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const char *name;
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const unsigned int *pins;
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unsigned int num_pins;
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const void *data;
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};
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/**
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* struct meson_pmx_func - a pinmux function
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*
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* @name: function name
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* @groups: groups in the function
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* @num_groups: number of groups in the function
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*/
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struct meson_pmx_func {
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const char *name;
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const char * const *groups;
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unsigned int num_groups;
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};
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/**
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* struct meson_reg_desc - a register descriptor
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*
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* @reg: register offset in the regmap
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* @bit: bit index in register
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*
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* The structure describes the information needed to control pull,
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* pull-enable, direction, etc. for a single pin
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*/
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struct meson_reg_desc {
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unsigned int reg;
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unsigned int bit;
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};
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/**
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* enum meson_reg_type - type of registers encoded in @meson_reg_desc
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*/
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enum meson_reg_type {
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REG_PULLEN,
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REG_PULL,
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REG_DIR,
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REG_OUT,
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REG_IN,
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REG_DS,
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NUM_REG,
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};
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/**
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* enum meson_pinconf_drv - value of drive-strength supported
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*/
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enum meson_pinconf_drv {
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MESON_PINCONF_DRV_500UA,
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MESON_PINCONF_DRV_2500UA,
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MESON_PINCONF_DRV_3000UA,
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MESON_PINCONF_DRV_4000UA,
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};
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/**
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* struct meson bank
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*
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* @name: bank name
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* @first: first pin of the bank
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* @last: last pin of the bank
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* @irq: hwirq base number of the bank
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* @regs: array of register descriptors
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*
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* A bank represents a set of pins controlled by a contiguous set of
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* bits in the domain registers. The structure specifies which bits in
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* the regmap control the different functionalities. Each member of
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* the @regs array refers to the first pin of the bank.
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*/
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struct meson_bank {
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const char *name;
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unsigned int first;
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unsigned int last;
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int irq_first;
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int irq_last;
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struct meson_reg_desc regs[NUM_REG];
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};
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struct meson_pinctrl_data {
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const char *name;
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const struct pinctrl_pin_desc *pins;
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struct meson_pmx_group *groups;
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struct meson_pmx_func *funcs;
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unsigned int num_pins;
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unsigned int num_groups;
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unsigned int num_funcs;
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struct meson_bank *banks;
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unsigned int num_banks;
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const struct pinmux_ops *pmx_ops;
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void *pmx_data;
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};
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struct meson_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pcdev;
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struct pinctrl_desc desc;
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struct meson_pinctrl_data *data;
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struct regmap *reg_mux;
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struct regmap *reg_pullen;
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struct regmap *reg_pull;
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struct regmap *reg_gpio;
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struct regmap *reg_ds;
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struct gpio_chip chip;
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struct device_node *of_node;
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};
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#define FUNCTION(fn) \
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{ \
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.name = #fn, \
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.groups = fn ## _groups, \
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.num_groups = ARRAY_SIZE(fn ## _groups), \
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}
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#define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \
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dsr, dsb) \
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{ \
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.name = n, \
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.first = f, \
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.last = l, \
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.irq_first = fi, \
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.irq_last = li, \
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.regs = { \
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[REG_PULLEN] = { per, peb }, \
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[REG_PULL] = { pr, pb }, \
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[REG_DIR] = { dr, db }, \
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[REG_OUT] = { or, ob }, \
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[REG_IN] = { ir, ib }, \
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[REG_DS] = { dsr, dsb }, \
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}, \
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}
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#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
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BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0)
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#define MESON_PIN(x) PINCTRL_PIN(x, #x)
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/* Common pmx functions */
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int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev);
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const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
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unsigned selector);
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int meson_pmx_get_groups(struct pinctrl_dev *pcdev,
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unsigned selector,
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const char * const **groups,
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unsigned * const num_groups);
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/* Common probe function */
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int meson_pinctrl_probe(struct platform_device *pdev);
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