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40ac9b196d
The Video Timing Controller (VTC) includes a timing detector and/or a timing generator. Only the generator is currently supported. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
381 lines
11 KiB
C
381 lines
11 KiB
C
/*
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* Xilinx Video Timing Controller
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*
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* Copyright (C) 2013-2015 Ideas on Board
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* Copyright (C) 2013-2015 Xilinx, Inc.
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*
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* Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "xilinx-vip.h"
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#include "xilinx-vtc.h"
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#define XVTC_CONTROL_FIELD_ID_POL_SRC (1 << 26)
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#define XVTC_CONTROL_ACTIVE_CHROMA_POL_SRC (1 << 25)
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#define XVTC_CONTROL_ACTIVE_VIDEO_POL_SRC (1 << 24)
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#define XVTC_CONTROL_HSYNC_POL_SRC (1 << 23)
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#define XVTC_CONTROL_VSYNC_POL_SRC (1 << 22)
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#define XVTC_CONTROL_HBLANK_POL_SRC (1 << 21)
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#define XVTC_CONTROL_VBLANK_POL_SRC (1 << 20)
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#define XVTC_CONTROL_CHROMA_SRC (1 << 18)
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#define XVTC_CONTROL_VBLANK_HOFF_SRC (1 << 17)
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#define XVTC_CONTROL_VSYNC_END_SRC (1 << 16)
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#define XVTC_CONTROL_VSYNC_START_SRC (1 << 15)
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#define XVTC_CONTROL_ACTIVE_VSIZE_SRC (1 << 14)
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#define XVTC_CONTROL_FRAME_VSIZE_SRC (1 << 13)
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#define XVTC_CONTROL_HSYNC_END_SRC (1 << 11)
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#define XVTC_CONTROL_HSYNC_START_SRC (1 << 10)
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#define XVTC_CONTROL_ACTIVE_HSIZE_SRC (1 << 9)
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#define XVTC_CONTROL_FRAME_HSIZE_SRC (1 << 8)
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#define XVTC_CONTROL_SYNC_ENABLE (1 << 5)
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#define XVTC_CONTROL_DET_ENABLE (1 << 3)
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#define XVTC_CONTROL_GEN_ENABLE (1 << 2)
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#define XVTC_STATUS_FSYNC(n) ((n) << 16)
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#define XVTC_STATUS_GEN_ACTIVE_VIDEO (1 << 13)
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#define XVTC_STATUS_GEN_VBLANK (1 << 12)
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#define XVTC_STATUS_DET_ACTIVE_VIDEO (1 << 11)
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#define XVTC_STATUS_DET_VBLANK (1 << 10)
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#define XVTC_STATUS_LOCK_LOSS (1 << 9)
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#define XVTC_STATUS_LOCK (1 << 8)
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#define XVTC_ERROR_ACTIVE_CHROMA_LOCK (1 << 21)
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#define XVTC_ERROR_ACTIVE_VIDEO_LOCK (1 << 20)
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#define XVTC_ERROR_HSYNC_LOCK (1 << 19)
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#define XVTC_ERROR_VSYNC_LOCK (1 << 18)
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#define XVTC_ERROR_HBLANK_LOCK (1 << 17)
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#define XVTC_ERROR_VBLANK_LOCK (1 << 16)
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#define XVTC_IRQ_ENABLE_FSYNC(n) ((n) << 16)
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#define XVTC_IRQ_ENABLE_GEN_ACTIVE_VIDEO (1 << 13)
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#define XVTC_IRQ_ENABLE_GEN_VBLANK (1 << 12)
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#define XVTC_IRQ_ENABLE_DET_ACTIVE_VIDEO (1 << 11)
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#define XVTC_IRQ_ENABLE_DET_VBLANK (1 << 10)
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#define XVTC_IRQ_ENABLE_LOCK_LOSS (1 << 9)
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#define XVTC_IRQ_ENABLE_LOCK (1 << 8)
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/*
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* The following registers exist in two blocks, one at 0x0020 for the detector
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* and one at 0x0060 for the generator.
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*/
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#define XVTC_DETECTOR_OFFSET 0x0020
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#define XVTC_GENERATOR_OFFSET 0x0060
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#define XVTC_ACTIVE_SIZE 0x0000
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#define XVTC_ACTIVE_VSIZE_SHIFT 16
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#define XVTC_ACTIVE_VSIZE_MASK (0x1fff << 16)
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#define XVTC_ACTIVE_HSIZE_SHIFT 0
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#define XVTC_ACTIVE_HSIZE_MASK (0x1fff << 0)
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#define XVTC_TIMING_STATUS 0x0004
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#define XVTC_TIMING_STATUS_ACTIVE_VIDEO (1 << 2)
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#define XVTC_TIMING_STATUS_VBLANK (1 << 1)
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#define XVTC_TIMING_STATUS_LOCKED (1 << 0)
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#define XVTC_ENCODING 0x0008
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#define XVTC_ENCODING_CHROMA_PARITY_SHIFT 8
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#define XVTC_ENCODING_CHROMA_PARITY_MASK (3 << 8)
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#define XVTC_ENCODING_CHROMA_PARITY_EVEN_ALL (0 << 8)
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#define XVTC_ENCODING_CHROMA_PARITY_ODD_ALL (1 << 8)
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#define XVTC_ENCODING_CHROMA_PARITY_EVEN_EVEN (2 << 8)
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#define XVTC_ENCODING_CHROMA_PARITY_ODD_EVEN (3 << 8)
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#define XVTC_ENCODING_VIDEO_FORMAT_SHIFT 0
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#define XVTC_ENCODING_VIDEO_FORMAT_MASK (0xf << 0)
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#define XVTC_ENCODING_VIDEO_FORMAT_YUV422 (0 << 0)
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#define XVTC_ENCODING_VIDEO_FORMAT_YUV444 (1 << 0)
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#define XVTC_ENCODING_VIDEO_FORMAT_RGB (2 << 0)
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#define XVTC_ENCODING_VIDEO_FORMAT_YUV420 (3 << 0)
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#define XVTC_POLARITY 0x000c
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#define XVTC_POLARITY_ACTIVE_CHROMA_POL (1 << 5)
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#define XVTC_POLARITY_ACTIVE_VIDEO_POL (1 << 4)
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#define XVTC_POLARITY_HSYNC_POL (1 << 3)
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#define XVTC_POLARITY_VSYNC_POL (1 << 2)
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#define XVTC_POLARITY_HBLANK_POL (1 << 1)
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#define XVTC_POLARITY_VBLANK_POL (1 << 0)
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#define XVTC_HSIZE 0x0010
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#define XVTC_HSIZE_MASK (0x1fff << 0)
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#define XVTC_VSIZE 0x0014
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#define XVTC_VSIZE_MASK (0x1fff << 0)
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#define XVTC_HSYNC 0x0018
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#define XVTC_HSYNC_END_SHIFT 16
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#define XVTC_HSYNC_END_MASK (0x1fff << 16)
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#define XVTC_HSYNC_START_SHIFT 0
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#define XVTC_HSYNC_START_MASK (0x1fff << 0)
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#define XVTC_F0_VBLANK_H 0x001c
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#define XVTC_F0_VBLANK_HEND_SHIFT 16
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#define XVTC_F0_VBLANK_HEND_MASK (0x1fff << 16)
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#define XVTC_F0_VBLANK_HSTART_SHIFT 0
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#define XVTC_F0_VBLANK_HSTART_MASK (0x1fff << 0)
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#define XVTC_F0_VSYNC_V 0x0020
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#define XVTC_F0_VSYNC_VEND_SHIFT 16
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#define XVTC_F0_VSYNC_VEND_MASK (0x1fff << 16)
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#define XVTC_F0_VSYNC_VSTART_SHIFT 0
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#define XVTC_F0_VSYNC_VSTART_MASK (0x1fff << 0)
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#define XVTC_F0_VSYNC_H 0x0024
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#define XVTC_F0_VSYNC_HEND_SHIFT 16
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#define XVTC_F0_VSYNC_HEND_MASK (0x1fff << 16)
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#define XVTC_F0_VSYNC_HSTART_SHIFT 0
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#define XVTC_F0_VSYNC_HSTART_MASK (0x1fff << 0)
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#define XVTC_FRAME_SYNC_CONFIG(n) (0x0100 + 4 * (n))
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#define XVTC_FRAME_SYNC_V_START_SHIFT 16
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#define XVTC_FRAME_SYNC_V_START_MASK (0x1fff << 16)
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#define XVTC_FRAME_SYNC_H_START_SHIFT 0
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#define XVTC_FRAME_SYNC_H_START_MASK (0x1fff << 0)
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#define XVTC_GENERATOR_GLOBAL_DELAY 0x0104
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/**
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* struct xvtc_device - Xilinx Video Timing Controller device structure
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* @xvip: Xilinx Video IP device
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* @list: entry in the global VTC list
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* @has_detector: the VTC has a timing detector
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* @has_generator: the VTC has a timing generator
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* @config: generator timings configuration
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*/
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struct xvtc_device {
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struct xvip_device xvip;
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struct list_head list;
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bool has_detector;
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bool has_generator;
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struct xvtc_config config;
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};
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static LIST_HEAD(xvtc_list);
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static DEFINE_MUTEX(xvtc_lock);
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static inline void xvtc_gen_write(struct xvtc_device *xvtc, u32 addr, u32 value)
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{
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xvip_write(&xvtc->xvip, XVTC_GENERATOR_OFFSET + addr, value);
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}
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/* -----------------------------------------------------------------------------
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* Generator Operations
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*/
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int xvtc_generator_start(struct xvtc_device *xvtc,
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const struct xvtc_config *config)
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{
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int ret;
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if (!xvtc->has_generator)
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return -ENXIO;
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ret = clk_prepare_enable(xvtc->xvip.clk);
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if (ret < 0)
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return ret;
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/* We don't care about the chroma active signal, encoding parameters are
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* not important for now.
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*/
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xvtc_gen_write(xvtc, XVTC_POLARITY,
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XVTC_POLARITY_ACTIVE_CHROMA_POL |
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XVTC_POLARITY_ACTIVE_VIDEO_POL |
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XVTC_POLARITY_HSYNC_POL | XVTC_POLARITY_VSYNC_POL |
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XVTC_POLARITY_HBLANK_POL | XVTC_POLARITY_VBLANK_POL);
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/* Hardcode the polarity to active high, as required by the video in to
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* AXI4-stream core.
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*/
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xvtc_gen_write(xvtc, XVTC_ENCODING, 0);
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/* Configure the timings. The VBLANK and VSYNC signals assertion and
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* deassertion are hardcoded to the first pixel of the line.
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*/
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xvtc_gen_write(xvtc, XVTC_ACTIVE_SIZE,
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(config->vblank_start << XVTC_ACTIVE_VSIZE_SHIFT) |
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(config->hblank_start << XVTC_ACTIVE_HSIZE_SHIFT));
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xvtc_gen_write(xvtc, XVTC_HSIZE, config->hsize);
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xvtc_gen_write(xvtc, XVTC_VSIZE, config->vsize);
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xvtc_gen_write(xvtc, XVTC_HSYNC,
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(config->hsync_end << XVTC_HSYNC_END_SHIFT) |
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(config->hsync_start << XVTC_HSYNC_START_SHIFT));
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xvtc_gen_write(xvtc, XVTC_F0_VBLANK_H, 0);
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xvtc_gen_write(xvtc, XVTC_F0_VSYNC_V,
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(config->vsync_end << XVTC_F0_VSYNC_VEND_SHIFT) |
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(config->vsync_start << XVTC_F0_VSYNC_VSTART_SHIFT));
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xvtc_gen_write(xvtc, XVTC_F0_VSYNC_H, 0);
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/* Enable the generator. Set the source of all generator parameters to
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* generator registers.
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*/
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xvip_write(&xvtc->xvip, XVIP_CTRL_CONTROL,
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XVTC_CONTROL_ACTIVE_CHROMA_POL_SRC |
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XVTC_CONTROL_ACTIVE_VIDEO_POL_SRC |
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XVTC_CONTROL_HSYNC_POL_SRC | XVTC_CONTROL_VSYNC_POL_SRC |
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XVTC_CONTROL_HBLANK_POL_SRC | XVTC_CONTROL_VBLANK_POL_SRC |
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XVTC_CONTROL_CHROMA_SRC | XVTC_CONTROL_VBLANK_HOFF_SRC |
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XVTC_CONTROL_VSYNC_END_SRC | XVTC_CONTROL_VSYNC_START_SRC |
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XVTC_CONTROL_ACTIVE_VSIZE_SRC |
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XVTC_CONTROL_FRAME_VSIZE_SRC | XVTC_CONTROL_HSYNC_END_SRC |
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XVTC_CONTROL_HSYNC_START_SRC |
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XVTC_CONTROL_ACTIVE_HSIZE_SRC |
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XVTC_CONTROL_FRAME_HSIZE_SRC | XVTC_CONTROL_GEN_ENABLE |
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XVIP_CTRL_CONTROL_REG_UPDATE);
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return 0;
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}
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EXPORT_SYMBOL_GPL(xvtc_generator_start);
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int xvtc_generator_stop(struct xvtc_device *xvtc)
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{
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if (!xvtc->has_generator)
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return -ENXIO;
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xvip_write(&xvtc->xvip, XVIP_CTRL_CONTROL, 0);
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clk_disable_unprepare(xvtc->xvip.clk);
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return 0;
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}
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EXPORT_SYMBOL_GPL(xvtc_generator_stop);
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struct xvtc_device *xvtc_of_get(struct device_node *np)
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{
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struct device_node *xvtc_node;
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struct xvtc_device *found = NULL;
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struct xvtc_device *xvtc;
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if (!of_find_property(np, "xlnx,vtc", NULL))
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return NULL;
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xvtc_node = of_parse_phandle(np, "xlnx,vtc", 0);
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if (xvtc_node == NULL)
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return ERR_PTR(-EINVAL);
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mutex_lock(&xvtc_lock);
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list_for_each_entry(xvtc, &xvtc_list, list) {
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if (xvtc->xvip.dev->of_node == xvtc_node) {
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found = xvtc;
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break;
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}
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}
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mutex_unlock(&xvtc_lock);
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of_node_put(xvtc_node);
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if (!found)
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return ERR_PTR(-EPROBE_DEFER);
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return found;
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}
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EXPORT_SYMBOL_GPL(xvtc_of_get);
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void xvtc_put(struct xvtc_device *xvtc)
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{
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}
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EXPORT_SYMBOL_GPL(xvtc_put);
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/* -----------------------------------------------------------------------------
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* Registration and Unregistration
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*/
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static void xvtc_register_device(struct xvtc_device *xvtc)
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{
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mutex_lock(&xvtc_lock);
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list_add_tail(&xvtc->list, &xvtc_list);
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mutex_unlock(&xvtc_lock);
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}
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static void xvtc_unregister_device(struct xvtc_device *xvtc)
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{
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mutex_lock(&xvtc_lock);
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list_del(&xvtc->list);
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mutex_unlock(&xvtc_lock);
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}
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/* -----------------------------------------------------------------------------
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* Platform Device Driver
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*/
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static int xvtc_parse_of(struct xvtc_device *xvtc)
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{
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struct device_node *node = xvtc->xvip.dev->of_node;
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xvtc->has_detector = of_property_read_bool(node, "xlnx,detector");
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xvtc->has_generator = of_property_read_bool(node, "xlnx,generator");
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return 0;
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}
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static int xvtc_probe(struct platform_device *pdev)
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{
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struct xvtc_device *xvtc;
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int ret;
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xvtc = devm_kzalloc(&pdev->dev, sizeof(*xvtc), GFP_KERNEL);
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if (!xvtc)
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return -ENOMEM;
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xvtc->xvip.dev = &pdev->dev;
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ret = xvtc_parse_of(xvtc);
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if (ret < 0)
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return ret;
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ret = xvip_init_resources(&xvtc->xvip);
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if (ret < 0)
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return ret;
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platform_set_drvdata(pdev, xvtc);
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xvip_print_version(&xvtc->xvip);
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xvtc_register_device(xvtc);
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return 0;
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}
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static int xvtc_remove(struct platform_device *pdev)
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{
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struct xvtc_device *xvtc = platform_get_drvdata(pdev);
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xvtc_unregister_device(xvtc);
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xvip_cleanup_resources(&xvtc->xvip);
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return 0;
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}
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static const struct of_device_id xvtc_of_id_table[] = {
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{ .compatible = "xlnx,v-tc-6.1" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, xvtc_of_id_table);
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static struct platform_driver xvtc_driver = {
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.driver = {
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.name = "xilinx-vtc",
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.of_match_table = xvtc_of_id_table,
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},
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.probe = xvtc_probe,
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.remove = xvtc_remove,
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};
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module_platform_driver(xvtc_driver);
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MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
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MODULE_DESCRIPTION("Xilinx Video Timing Controller Driver");
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MODULE_LICENSE("GPL v2");
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