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	 e41752c0e7
			
		
	
	
		e41752c0e7
		
	
	
	
	
		
			
			Use uart_circ_empty() instead of open-coding it via xmit->head & tail. Use preexisting mcf_stop_tx() to avoid stop-tx code duplication. Signed-off-by: Jiri Slaby <jslaby@suse.cz> Link: https://lore.kernel.org/r/20220124071430.14907-12-jslaby@suse.cz Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
		
			
				
	
	
		
			704 lines
		
	
	
		
			18 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			704 lines
		
	
	
		
			18 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /****************************************************************************/
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| 
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| /*
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|  *	mcf.c -- Freescale ColdFire UART driver
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|  *
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|  *	(C) Copyright 2003-2007, Greg Ungerer <gerg@uclinux.org>
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|  */
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| 
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| /****************************************************************************/
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| 
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| #include <linux/kernel.h>
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| #include <linux/init.h>
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| #include <linux/interrupt.h>
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| #include <linux/module.h>
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| #include <linux/console.h>
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| #include <linux/tty.h>
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| #include <linux/tty_flip.h>
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| #include <linux/serial.h>
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| #include <linux/serial_core.h>
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| #include <linux/io.h>
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| #include <linux/uaccess.h>
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| #include <linux/platform_device.h>
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| #include <asm/coldfire.h>
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| #include <asm/mcfsim.h>
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| #include <asm/mcfuart.h>
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| #include <asm/nettel.h>
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| 
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| /****************************************************************************/
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| 
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| /*
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|  *	Some boards implement the DTR/DCD lines using GPIO lines, most
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|  *	don't. Dummy out the access macros for those that don't. Those
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|  *	that do should define these macros somewhere in there board
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|  *	specific inlude files.
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|  */
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| #if !defined(mcf_getppdcd)
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| #define	mcf_getppdcd(p)		(1)
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| #endif
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| #if !defined(mcf_getppdtr)
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| #define	mcf_getppdtr(p)		(1)
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| #endif
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| #if !defined(mcf_setppdtr)
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| #define	mcf_setppdtr(p, v)	do { } while (0)
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| #endif
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| 
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| /****************************************************************************/
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| 
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| /*
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|  *	Local per-uart structure.
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|  */
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| struct mcf_uart {
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| 	struct uart_port	port;
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| 	unsigned int		sigs;		/* Local copy of line sigs */
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| 	unsigned char		imr;		/* Local IMR mirror */
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| };
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| 
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| /****************************************************************************/
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| 
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| static unsigned int mcf_tx_empty(struct uart_port *port)
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| {
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| 	return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
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| 		TIOCSER_TEMT : 0;
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| }
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| 
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| /****************************************************************************/
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| 
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| static unsigned int mcf_get_mctrl(struct uart_port *port)
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| {
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| 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
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| 	unsigned int sigs;
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| 
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| 	sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
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| 		0 : TIOCM_CTS;
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| 	sigs |= (pp->sigs & TIOCM_RTS);
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| 	sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
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| 	sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
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| 
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| 	return sigs;
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
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| {
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| 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
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| 
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| 	pp->sigs = sigs;
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| 	mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
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| 	if (sigs & TIOCM_RTS)
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| 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
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| 	else
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| 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_start_tx(struct uart_port *port)
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| {
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| 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
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| 
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| 	if (port->rs485.flags & SER_RS485_ENABLED) {
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| 		/* Enable Transmitter */
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| 		writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
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| 		/* Manually assert RTS */
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| 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
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| 	}
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| 	pp->imr |= MCFUART_UIR_TXREADY;
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| 	writeb(pp->imr, port->membase + MCFUART_UIMR);
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_stop_tx(struct uart_port *port)
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| {
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| 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
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| 
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| 	pp->imr &= ~MCFUART_UIR_TXREADY;
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| 	writeb(pp->imr, port->membase + MCFUART_UIMR);
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_stop_rx(struct uart_port *port)
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| {
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| 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
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| 
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| 	pp->imr &= ~MCFUART_UIR_RXREADY;
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| 	writeb(pp->imr, port->membase + MCFUART_UIMR);
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_break_ctl(struct uart_port *port, int break_state)
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| {
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| 	unsigned long flags;
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| 
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| 	spin_lock_irqsave(&port->lock, flags);
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| 	if (break_state == -1)
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| 		writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
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| 	else
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| 		writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
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| 	spin_unlock_irqrestore(&port->lock, flags);
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| }
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| 
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| /****************************************************************************/
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| 
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| static int mcf_startup(struct uart_port *port)
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| {
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| 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
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| 	unsigned long flags;
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| 
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| 	spin_lock_irqsave(&port->lock, flags);
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| 
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| 	/* Reset UART, get it into known state... */
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| 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
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| 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
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| 
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| 	/* Enable the UART transmitter and receiver */
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| 	writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
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| 		port->membase + MCFUART_UCR);
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| 
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| 	/* Enable RX interrupts now */
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| 	pp->imr = MCFUART_UIR_RXREADY;
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| 	writeb(pp->imr, port->membase + MCFUART_UIMR);
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| 
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| 	spin_unlock_irqrestore(&port->lock, flags);
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| 
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| 	return 0;
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_shutdown(struct uart_port *port)
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| {
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| 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
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| 	unsigned long flags;
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| 
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| 	spin_lock_irqsave(&port->lock, flags);
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| 
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| 	/* Disable all interrupts now */
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| 	pp->imr = 0;
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| 	writeb(pp->imr, port->membase + MCFUART_UIMR);
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| 
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| 	/* Disable UART transmitter and receiver */
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| 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
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| 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
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| 
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| 	spin_unlock_irqrestore(&port->lock, flags);
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
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| 	struct ktermios *old)
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| {
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| 	unsigned long flags;
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| 	unsigned int baud, baudclk;
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| #if defined(CONFIG_M5272)
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| 	unsigned int baudfr;
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| #endif
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| 	unsigned char mr1, mr2;
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| 
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| 	baud = uart_get_baud_rate(port, termios, old, 0, 230400);
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| #if defined(CONFIG_M5272)
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| 	baudclk = (MCF_BUSCLK / baud) / 32;
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| 	baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
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| #else
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| 	baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
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| #endif
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| 
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| 	mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
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| 	mr2 = 0;
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| 
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| 	switch (termios->c_cflag & CSIZE) {
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| 	case CS5: mr1 |= MCFUART_MR1_CS5; break;
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| 	case CS6: mr1 |= MCFUART_MR1_CS6; break;
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| 	case CS7: mr1 |= MCFUART_MR1_CS7; break;
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| 	case CS8:
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| 	default:  mr1 |= MCFUART_MR1_CS8; break;
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| 	}
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| 
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| 	if (termios->c_cflag & PARENB) {
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| 		if (termios->c_cflag & CMSPAR) {
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| 			if (termios->c_cflag & PARODD)
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| 				mr1 |= MCFUART_MR1_PARITYMARK;
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| 			else
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| 				mr1 |= MCFUART_MR1_PARITYSPACE;
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| 		} else {
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| 			if (termios->c_cflag & PARODD)
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| 				mr1 |= MCFUART_MR1_PARITYODD;
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| 			else
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| 				mr1 |= MCFUART_MR1_PARITYEVEN;
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| 		}
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| 	} else {
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| 		mr1 |= MCFUART_MR1_PARITYNONE;
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| 	}
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| 
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| 	/*
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| 	 * FIXME: port->read_status_mask and port->ignore_status_mask
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| 	 * need to be initialized based on termios settings for
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| 	 * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
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| 	 */
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| 
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| 	if (termios->c_cflag & CSTOPB)
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| 		mr2 |= MCFUART_MR2_STOP2;
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| 	else
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| 		mr2 |= MCFUART_MR2_STOP1;
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| 
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| 	if (termios->c_cflag & CRTSCTS) {
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| 		mr1 |= MCFUART_MR1_RXRTS;
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| 		mr2 |= MCFUART_MR2_TXCTS;
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| 	}
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| 
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| 	spin_lock_irqsave(&port->lock, flags);
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| 	if (port->rs485.flags & SER_RS485_ENABLED) {
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| 		dev_dbg(port->dev, "Setting UART to RS485\n");
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| 		mr2 |= MCFUART_MR2_TXRTS;
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| 	}
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| 
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| 	uart_update_timeout(port, termios->c_cflag, baud);
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| 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
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| 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
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| 	writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
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| 	writeb(mr1, port->membase + MCFUART_UMR);
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| 	writeb(mr2, port->membase + MCFUART_UMR);
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| 	writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
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| 	writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
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| #if defined(CONFIG_M5272)
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| 	writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
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| #endif
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| 	writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
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| 		port->membase + MCFUART_UCSR);
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| 	writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
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| 		port->membase + MCFUART_UCR);
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| 	spin_unlock_irqrestore(&port->lock, flags);
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_rx_chars(struct mcf_uart *pp)
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| {
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| 	struct uart_port *port = &pp->port;
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| 	unsigned char status, ch, flag;
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| 
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| 	while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
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| 		ch = readb(port->membase + MCFUART_URB);
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| 		flag = TTY_NORMAL;
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| 		port->icount.rx++;
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| 
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| 		if (status & MCFUART_USR_RXERR) {
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| 			writeb(MCFUART_UCR_CMDRESETERR,
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| 				port->membase + MCFUART_UCR);
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| 
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| 			if (status & MCFUART_USR_RXBREAK) {
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| 				port->icount.brk++;
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| 				if (uart_handle_break(port))
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| 					continue;
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| 			} else if (status & MCFUART_USR_RXPARITY) {
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| 				port->icount.parity++;
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| 			} else if (status & MCFUART_USR_RXOVERRUN) {
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| 				port->icount.overrun++;
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| 			} else if (status & MCFUART_USR_RXFRAMING) {
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| 				port->icount.frame++;
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| 			}
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| 
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| 			status &= port->read_status_mask;
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| 
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| 			if (status & MCFUART_USR_RXBREAK)
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| 				flag = TTY_BREAK;
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| 			else if (status & MCFUART_USR_RXPARITY)
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| 				flag = TTY_PARITY;
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| 			else if (status & MCFUART_USR_RXFRAMING)
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| 				flag = TTY_FRAME;
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| 		}
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| 
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| 		if (uart_handle_sysrq_char(port, ch))
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| 			continue;
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| 		uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
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| 	}
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| 
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| 	tty_flip_buffer_push(&port->state->port);
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_tx_chars(struct mcf_uart *pp)
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| {
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| 	struct uart_port *port = &pp->port;
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| 	struct circ_buf *xmit = &port->state->xmit;
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| 
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| 	if (port->x_char) {
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| 		/* Send special char - probably flow control */
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| 		writeb(port->x_char, port->membase + MCFUART_UTB);
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| 		port->x_char = 0;
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| 		port->icount.tx++;
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| 		return;
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| 	}
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| 
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| 	while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
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| 		if (uart_circ_empty(xmit))
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| 			break;
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| 		writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
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| 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
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| 		port->icount.tx++;
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| 	}
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| 
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| 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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| 		uart_write_wakeup(port);
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| 
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| 	if (uart_circ_empty(xmit)) {
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| 		mcf_stop_tx(port);
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| 		/* Disable TX to negate RTS automatically */
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| 		if (port->rs485.flags & SER_RS485_ENABLED)
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| 			writeb(MCFUART_UCR_TXDISABLE,
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| 				port->membase + MCFUART_UCR);
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| 	}
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| }
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| 
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| /****************************************************************************/
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| 
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| static irqreturn_t mcf_interrupt(int irq, void *data)
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| {
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| 	struct uart_port *port = data;
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| 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
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| 	unsigned int isr;
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| 	irqreturn_t ret = IRQ_NONE;
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| 
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| 	isr = readb(port->membase + MCFUART_UISR) & pp->imr;
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| 
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| 	spin_lock(&port->lock);
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| 	if (isr & MCFUART_UIR_RXREADY) {
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| 		mcf_rx_chars(pp);
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| 		ret = IRQ_HANDLED;
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| 	}
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| 	if (isr & MCFUART_UIR_TXREADY) {
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| 		mcf_tx_chars(pp);
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| 		ret = IRQ_HANDLED;
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| 	}
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| 	spin_unlock(&port->lock);
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| 
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| 	return ret;
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_config_port(struct uart_port *port, int flags)
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| {
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| 	port->type = PORT_MCF;
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| 	port->fifosize = MCFUART_TXFIFOSIZE;
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| 
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| 	/* Clear mask, so no surprise interrupts. */
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| 	writeb(0, port->membase + MCFUART_UIMR);
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| 
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| 	if (request_irq(port->irq, mcf_interrupt, 0, "UART", port))
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| 		printk(KERN_ERR "MCF: unable to attach ColdFire UART %d "
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| 			"interrupt vector=%d\n", port->line, port->irq);
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| }
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| 
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| /****************************************************************************/
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| 
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| static const char *mcf_type(struct uart_port *port)
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| {
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| 	return (port->type == PORT_MCF) ? "ColdFire UART" : NULL;
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| }
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| 
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| /****************************************************************************/
 | |
| 
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| static int mcf_request_port(struct uart_port *port)
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| {
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| 	/* UARTs always present */
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| 	return 0;
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| }
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| 
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| /****************************************************************************/
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| 
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| static void mcf_release_port(struct uart_port *port)
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| {
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| 	/* Nothing to release... */
 | |
| }
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| 
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| /****************************************************************************/
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| 
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| static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
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| {
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| 	if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
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| 		return -EINVAL;
 | |
| 	return 0;
 | |
| }
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| 
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| /****************************************************************************/
 | |
| 
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| /* Enable or disable the RS485 support */
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| static int mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
 | |
| {
 | |
| 	unsigned char mr1, mr2;
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| 
 | |
| 	/* Get mode registers */
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| 	mr1 = readb(port->membase + MCFUART_UMR);
 | |
| 	mr2 = readb(port->membase + MCFUART_UMR);
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| 	if (rs485->flags & SER_RS485_ENABLED) {
 | |
| 		dev_dbg(port->dev, "Setting UART to RS485\n");
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| 		/* Automatically negate RTS after TX completes */
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| 		mr2 |= MCFUART_MR2_TXRTS;
 | |
| 	} else {
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| 		dev_dbg(port->dev, "Setting UART to RS232\n");
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| 		mr2 &= ~MCFUART_MR2_TXRTS;
 | |
| 	}
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| 	writeb(mr1, port->membase + MCFUART_UMR);
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| 	writeb(mr2, port->membase + MCFUART_UMR);
 | |
| 	port->rs485 = *rs485;
 | |
| 
 | |
| 	return 0;
 | |
| }
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| /*
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|  *	Define the basic serial functions we support.
 | |
|  */
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| static const struct uart_ops mcf_uart_ops = {
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| 	.tx_empty	= mcf_tx_empty,
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| 	.get_mctrl	= mcf_get_mctrl,
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| 	.set_mctrl	= mcf_set_mctrl,
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| 	.start_tx	= mcf_start_tx,
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| 	.stop_tx	= mcf_stop_tx,
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| 	.stop_rx	= mcf_stop_rx,
 | |
| 	.break_ctl	= mcf_break_ctl,
 | |
| 	.startup	= mcf_startup,
 | |
| 	.shutdown	= mcf_shutdown,
 | |
| 	.set_termios	= mcf_set_termios,
 | |
| 	.type		= mcf_type,
 | |
| 	.request_port	= mcf_request_port,
 | |
| 	.release_port	= mcf_release_port,
 | |
| 	.config_port	= mcf_config_port,
 | |
| 	.verify_port	= mcf_verify_port,
 | |
| };
 | |
| 
 | |
| static struct mcf_uart mcf_ports[4];
 | |
| 
 | |
| #define	MCF_MAXPORTS	ARRAY_SIZE(mcf_ports)
 | |
| 
 | |
| /****************************************************************************/
 | |
| #if defined(CONFIG_SERIAL_MCF_CONSOLE)
 | |
| /****************************************************************************/
 | |
| 
 | |
| int __init early_mcf_setup(struct mcf_platform_uart *platp)
 | |
| {
 | |
| 	struct uart_port *port;
 | |
| 	int i;
 | |
| 
 | |
| 	for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
 | |
| 		port = &mcf_ports[i].port;
 | |
| 
 | |
| 		port->line = i;
 | |
| 		port->type = PORT_MCF;
 | |
| 		port->mapbase = platp[i].mapbase;
 | |
| 		port->membase = (platp[i].membase) ? platp[i].membase :
 | |
| 			(unsigned char __iomem *) port->mapbase;
 | |
| 		port->iotype = SERIAL_IO_MEM;
 | |
| 		port->irq = platp[i].irq;
 | |
| 		port->uartclk = MCF_BUSCLK;
 | |
| 		port->flags = UPF_BOOT_AUTOCONF;
 | |
| 		port->rs485_config = mcf_config_rs485;
 | |
| 		port->ops = &mcf_uart_ops;
 | |
| 	}
 | |
| 
 | |
| 	return 0;
 | |
| }
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| static void mcf_console_putc(struct console *co, const char c)
 | |
| {
 | |
| 	struct uart_port *port = &(mcf_ports + co->index)->port;
 | |
| 	int i;
 | |
| 
 | |
| 	for (i = 0; (i < 0x10000); i++) {
 | |
| 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
 | |
| 			break;
 | |
| 	}
 | |
| 	writeb(c, port->membase + MCFUART_UTB);
 | |
| 	for (i = 0; (i < 0x10000); i++) {
 | |
| 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
 | |
| 			break;
 | |
| 	}
 | |
| }
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| static void mcf_console_write(struct console *co, const char *s, unsigned int count)
 | |
| {
 | |
| 	for (; (count); count--, s++) {
 | |
| 		mcf_console_putc(co, *s);
 | |
| 		if (*s == '\n')
 | |
| 			mcf_console_putc(co, '\r');
 | |
| 	}
 | |
| }
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| static int __init mcf_console_setup(struct console *co, char *options)
 | |
| {
 | |
| 	struct uart_port *port;
 | |
| 	int baud = CONFIG_SERIAL_MCF_BAUDRATE;
 | |
| 	int bits = 8;
 | |
| 	int parity = 'n';
 | |
| 	int flow = 'n';
 | |
| 
 | |
| 	if ((co->index < 0) || (co->index >= MCF_MAXPORTS))
 | |
| 		co->index = 0;
 | |
| 	port = &mcf_ports[co->index].port;
 | |
| 	if (port->membase == 0)
 | |
| 		return -ENODEV;
 | |
| 
 | |
| 	if (options)
 | |
| 		uart_parse_options(options, &baud, &parity, &bits, &flow);
 | |
| 
 | |
| 	return uart_set_options(port, co, baud, parity, bits, flow);
 | |
| }
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| static struct uart_driver mcf_driver;
 | |
| 
 | |
| static struct console mcf_console = {
 | |
| 	.name		= "ttyS",
 | |
| 	.write		= mcf_console_write,
 | |
| 	.device		= uart_console_device,
 | |
| 	.setup		= mcf_console_setup,
 | |
| 	.flags		= CON_PRINTBUFFER,
 | |
| 	.index		= -1,
 | |
| 	.data		= &mcf_driver,
 | |
| };
 | |
| 
 | |
| static int __init mcf_console_init(void)
 | |
| {
 | |
| 	register_console(&mcf_console);
 | |
| 	return 0;
 | |
| }
 | |
| 
 | |
| console_initcall(mcf_console_init);
 | |
| 
 | |
| #define	MCF_CONSOLE	&mcf_console
 | |
| 
 | |
| /****************************************************************************/
 | |
| #else
 | |
| /****************************************************************************/
 | |
| 
 | |
| #define	MCF_CONSOLE	NULL
 | |
| 
 | |
| /****************************************************************************/
 | |
| #endif /* CONFIG_SERIAL_MCF_CONSOLE */
 | |
| /****************************************************************************/
 | |
| 
 | |
| /*
 | |
|  *	Define the mcf UART driver structure.
 | |
|  */
 | |
| static struct uart_driver mcf_driver = {
 | |
| 	.owner		= THIS_MODULE,
 | |
| 	.driver_name	= "mcf",
 | |
| 	.dev_name	= "ttyS",
 | |
| 	.major		= TTY_MAJOR,
 | |
| 	.minor		= 64,
 | |
| 	.nr		= MCF_MAXPORTS,
 | |
| 	.cons		= MCF_CONSOLE,
 | |
| };
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| static int mcf_probe(struct platform_device *pdev)
 | |
| {
 | |
| 	struct mcf_platform_uart *platp = dev_get_platdata(&pdev->dev);
 | |
| 	struct uart_port *port;
 | |
| 	int i;
 | |
| 
 | |
| 	for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
 | |
| 		port = &mcf_ports[i].port;
 | |
| 
 | |
| 		port->line = i;
 | |
| 		port->type = PORT_MCF;
 | |
| 		port->mapbase = platp[i].mapbase;
 | |
| 		port->membase = (platp[i].membase) ? platp[i].membase :
 | |
| 			(unsigned char __iomem *) platp[i].mapbase;
 | |
| 		port->dev = &pdev->dev;
 | |
| 		port->iotype = SERIAL_IO_MEM;
 | |
| 		port->irq = platp[i].irq;
 | |
| 		port->uartclk = MCF_BUSCLK;
 | |
| 		port->ops = &mcf_uart_ops;
 | |
| 		port->flags = UPF_BOOT_AUTOCONF;
 | |
| 		port->rs485_config = mcf_config_rs485;
 | |
| 		port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MCF_CONSOLE);
 | |
| 
 | |
| 		uart_add_one_port(&mcf_driver, port);
 | |
| 	}
 | |
| 
 | |
| 	return 0;
 | |
| }
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| static int mcf_remove(struct platform_device *pdev)
 | |
| {
 | |
| 	struct uart_port *port;
 | |
| 	int i;
 | |
| 
 | |
| 	for (i = 0; (i < MCF_MAXPORTS); i++) {
 | |
| 		port = &mcf_ports[i].port;
 | |
| 		if (port)
 | |
| 			uart_remove_one_port(&mcf_driver, port);
 | |
| 	}
 | |
| 
 | |
| 	return 0;
 | |
| }
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| static struct platform_driver mcf_platform_driver = {
 | |
| 	.probe		= mcf_probe,
 | |
| 	.remove		= mcf_remove,
 | |
| 	.driver		= {
 | |
| 		.name	= "mcfuart",
 | |
| 	},
 | |
| };
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| static int __init mcf_init(void)
 | |
| {
 | |
| 	int rc;
 | |
| 
 | |
| 	printk("ColdFire internal UART serial driver\n");
 | |
| 
 | |
| 	rc = uart_register_driver(&mcf_driver);
 | |
| 	if (rc)
 | |
| 		return rc;
 | |
| 	rc = platform_driver_register(&mcf_platform_driver);
 | |
| 	if (rc) {
 | |
| 		uart_unregister_driver(&mcf_driver);
 | |
| 		return rc;
 | |
| 	}
 | |
| 	return 0;
 | |
| }
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| static void __exit mcf_exit(void)
 | |
| {
 | |
| 	platform_driver_unregister(&mcf_platform_driver);
 | |
| 	uart_unregister_driver(&mcf_driver);
 | |
| }
 | |
| 
 | |
| /****************************************************************************/
 | |
| 
 | |
| module_init(mcf_init);
 | |
| module_exit(mcf_exit);
 | |
| 
 | |
| MODULE_AUTHOR("Greg Ungerer <gerg@uclinux.org>");
 | |
| MODULE_DESCRIPTION("Freescale ColdFire UART driver");
 | |
| MODULE_LICENSE("GPL");
 | |
| MODULE_ALIAS("platform:mcfuart");
 | |
| 
 | |
| /****************************************************************************/
 |