Michael Strauss 72f5b5a308 drm/amd/display: Check for null fclk voltage when parsing clock table ... [WHY] In cases where a clock table is malformed such that fclk entries have frequencies but not voltages listed, we don't catch the error and set clocks to 0 instead of using hardcoded values as we should. [HOW] Add check for clock tables fclk entry's voltage as well Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2020-04-07 14:22:10 -04:00
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dce100	drm/amd/display: move dispclk vco freq to clk mgr base	2019-10-25 16:50:08 -04:00
dce110	drm/amdgpu/display: fix 64 bit divide	2019-10-03 09:11:00 -05:00
dce112	drm/amd/display: rename core_dc to dc	2019-12-05 16:26:39 -05:00
dce120	drm/amd/display: Copy max_clks_by_state after dce_clk_mgr_construct	2019-07-18 14:18:09 -05:00
dcn10	drm/amd/display: rename core_dc to dc	2019-12-05 16:26:39 -05:00
dcn20	drm/amd/display: DPP DTO isn't update properly.	2020-03-19 00:03:04 -04:00
dcn21	drm/amd/display: Check for null fclk voltage when parsing clock table	2020-04-07 14:22:10 -04:00
clk_mgr.c	drm/amd/display: Fix RV2 Variant Detection	2020-02-25 11:09:12 -05:00
Makefile	amdgpu: Prevent build errors regarding soft/hard-float FP ABI tags	2020-02-11 15:35:22 -05:00