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c80dfd9bf5
Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Pan Wen <wenpan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/*
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* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __DTS_HI3516CV300_CLOCK_H
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#define __DTS_HI3516CV300_CLOCK_H
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/* hi3516CV300 core CRG */
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#define HI3516CV300_APB_CLK 0
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#define HI3516CV300_UART0_CLK 1
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#define HI3516CV300_UART1_CLK 2
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#define HI3516CV300_UART2_CLK 3
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#define HI3516CV300_SPI0_CLK 4
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#define HI3516CV300_SPI1_CLK 5
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#define HI3516CV300_FMC_CLK 6
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#define HI3516CV300_MMC0_CLK 7
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#define HI3516CV300_MMC1_CLK 8
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#define HI3516CV300_MMC2_CLK 9
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#define HI3516CV300_MMC3_CLK 10
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#define HI3516CV300_ETH_CLK 11
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#define HI3516CV300_ETH_MACIF_CLK 12
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#define HI3516CV300_DMAC_CLK 13
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#define HI3516CV300_PWM_CLK 14
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#define HI3516CV300_USB2_BUS_CLK 15
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#define HI3516CV300_USB2_OHCI48M_CLK 16
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#define HI3516CV300_USB2_OHCI12M_CLK 17
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#define HI3516CV300_USB2_OTG_UTMI_CLK 18
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#define HI3516CV300_USB2_HST_PHY_CLK 19
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#define HI3516CV300_USB2_UTMI0_CLK 20
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#define HI3516CV300_USB2_PHY_CLK 21
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/* hi3516CV300 sysctrl CRG */
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#define HI3516CV300_WDT_CLK 1
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#endif /* __DTS_HI3516CV300_CLOCK_H */
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