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	 f15cbe6f1a
			
		
	
	
		f15cbe6f1a
		
	
	
	
	
		
			
			This follows the sparc changes a439fe51a1.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
		
	
			
		
			
				
	
	
		
			44 lines
		
	
	
		
			1.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			44 lines
		
	
	
		
			1.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * include/asm-sh/cpu-sh3/cache.h
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|  *
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|  * Copyright (C) 1999 Niibe Yutaka
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|  *
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|  * This file is subject to the terms and conditions of the GNU General Public
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|  * License.  See the file "COPYING" in the main directory of this archive
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|  * for more details.
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|  */
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| #ifndef __ASM_CPU_SH3_CACHE_H
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| #define __ASM_CPU_SH3_CACHE_H
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| 
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| #define L1_CACHE_SHIFT	4
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| 
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| #define SH_CACHE_VALID		1
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| #define SH_CACHE_UPDATED	2
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| #define SH_CACHE_COMBINED	4
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| #define SH_CACHE_ASSOC		8
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| 
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| #define CCR		0xffffffec	/* Address of Cache Control Register */
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| 
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| #define CCR_CACHE_CE	0x01	/* Cache Enable */
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| #define CCR_CACHE_WT	0x02	/* Write-Through (for P0,U0,P3) (else writeback) */
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| #define CCR_CACHE_CB	0x04	/* Write-Back (for P1) (else writethrough) */
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| #define CCR_CACHE_CF	0x08	/* Cache Flush */
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| #define CCR_CACHE_ORA	0x20	/* RAM mode */
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| 
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| #define CACHE_OC_ADDRESS_ARRAY	0xf0000000
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| #define CACHE_PHYSADDR_MASK	0x1ffffc00
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| 
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| #define CCR_CACHE_ENABLE	CCR_CACHE_CE
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| #define CCR_CACHE_INVALIDATE	CCR_CACHE_CF
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| 
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| #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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|     defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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|     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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|     defined(CONFIG_CPU_SUBTYPE_SH7721)
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| #define CCR3_REG	0xa40000b4
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| #define CCR_CACHE_16KB  0x00010000
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| #define CCR_CACHE_32KB	0x00020000
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| #endif
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| 
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| #endif /* __ASM_CPU_SH3_CACHE_H */
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