Daire McNamara 1390a33b3d PCI: microchip: Set inbound address translation for coherent or non-coherent mode ... On Microchip PolarFire SoC the PCIe Root Port can be behind one of three general purpose Fabric Interface Controller (FIC) buses that encapsulates an AXI-S bus. Depending on which FIC(s) the Root Port is connected through to CPU space, and what address translation is done by that FIC, the Root Port driver's inbound address translation may vary. For all current supported designs and all future expected designs, inbound address translation done by a FIC on PolarFire SoC varies depending on whether PolarFire SoC is operating in coherent DMA mode or noncoherent DMA mode. The setup of the outbound address translation tables in the Root Port driver only needs to handle these two cases. Setup the inbound address translation tables to one of two address translations, depending on whether the Root Port is being used with coherent DMA or noncoherent DMA. Link: https://lore.kernel.org/r/20241011140043.1250030-3-daire.mcnamara@microchip.com Fixes: 6f15a9c9f9 ("PCI: microchip: Add Microchip PolarFire PCIe controller driver") Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> [bhelgaas: adapt for ac7f53b7e7 ("PCI: microchip: Add support for using either Root Port 1 or 2")] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>		2025-01-21 17:34:56 -06:00
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Kconfig	PCI: starfive: Add JH7110 PCIe controller	2024-05-28 11:15:30 -05:00
Makefile	PCI: starfive: Add JH7110 PCIe controller	2024-05-28 11:15:30 -05:00
pcie-microchip-host.c	PCI: microchip: Set inbound address translation for coherent or non-coherent mode	2025-01-21 17:34:56 -06:00
pcie-plda-host.c	PCI: microchip: Set inbound address translation for coherent or non-coherent mode	2025-01-21 17:34:56 -06:00
pcie-plda.h	PCI: microchip: Set inbound address translation for coherent or non-coherent mode	2025-01-21 17:34:56 -06:00
pcie-starfive.c	Merge branch 'pci/pm'	2024-11-25 13:40:46 -06:00