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8ca606de76
We observe black lines (underflow) on display when playing a 4K video with UVD. On Disabling Low memory P state this issue is not seen. In this patch ,disabling low memory P state only when video size >= 4k. Multiple runs of power measurement shows no impact Signed-off-by: suresh guttula <suresh.guttula@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
90 lines
3.4 KiB
C
90 lines
3.4 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_UVD_H__
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#define __AMDGPU_UVD_H__
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#define AMDGPU_DEFAULT_UVD_HANDLES 10
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#define AMDGPU_MAX_UVD_HANDLES 40
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#define AMDGPU_UVD_STACK_SIZE (200*1024)
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#define AMDGPU_UVD_HEAP_SIZE (256*1024)
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#define AMDGPU_UVD_SESSION_SIZE (50*1024)
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#define AMDGPU_UVD_FIRMWARE_OFFSET 256
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#define AMDGPU_MAX_UVD_INSTANCES 2
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#define AMDGPU_UVD_FIRMWARE_SIZE(adev) \
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(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \
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8) - AMDGPU_UVD_FIRMWARE_OFFSET)
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struct amdgpu_uvd_inst {
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struct amdgpu_bo *vcpu_bo;
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void *cpu_addr;
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uint64_t gpu_addr;
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void *saved_bo;
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struct amdgpu_ring ring;
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struct amdgpu_ring ring_enc[AMDGPU_MAX_UVD_ENC_RINGS];
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struct amdgpu_irq_src irq;
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uint32_t srbm_soft_reset;
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};
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#define AMDGPU_UVD_HARVEST_UVD0 (1 << 0)
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#define AMDGPU_UVD_HARVEST_UVD1 (1 << 1)
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struct amdgpu_uvd {
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const struct firmware *fw; /* UVD firmware */
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unsigned fw_version;
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unsigned max_handles;
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unsigned num_enc_rings;
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uint8_t num_uvd_inst;
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bool address_64_bit;
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bool use_ctx_buf;
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struct amdgpu_uvd_inst inst[AMDGPU_MAX_UVD_INSTANCES];
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struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
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atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
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struct drm_sched_entity entity;
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struct delayed_work idle_work;
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unsigned harvest_config;
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/* store image width to adjust nb memory state */
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unsigned decode_image_width;
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};
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int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
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int amdgpu_uvd_sw_fini(struct amdgpu_device *adev);
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int amdgpu_uvd_entity_init(struct amdgpu_device *adev);
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int amdgpu_uvd_suspend(struct amdgpu_device *adev);
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int amdgpu_uvd_resume(struct amdgpu_device *adev);
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int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
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struct dma_fence **fence);
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int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
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bool direct, struct dma_fence **fence);
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void amdgpu_uvd_free_handles(struct amdgpu_device *adev,
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struct drm_file *filp);
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int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx);
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void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring);
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void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring);
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int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev);
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#endif
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