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1996970773
Most platforms with a Mali-400 or Mali-450 GPU also have support for changing the GPU clock frequency. Add devfreq support so the GPU clock rate is updated based on the actual GPU usage when the "operating-points-v2" property is present in the board.dts. The actual devfreq code is taken from panfrost_devfreq.c and modified so it matches what the lima hardware needs: - a call to dev_pm_opp_set_clkname() during initialization because there are two clocks on Mali-4x0 IPs. "core" is the one that actually clocks the GPU so we need to control it using devfreq. - locking when reading or writing the devfreq statistics because (unlike than panfrost) we have multiple PP and GP IRQs which may finish jobs concurrently. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200319203427.2259891-3-martin.blumenstingl@googlemail.com
118 lines
2.7 KiB
C
118 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
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#ifndef __LIMA_SCHED_H__
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#define __LIMA_SCHED_H__
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#include <drm/gpu_scheduler.h>
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#include <linux/list.h>
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#include <linux/xarray.h>
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struct lima_device;
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struct lima_vm;
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struct lima_sched_error_task {
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struct list_head list;
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void *data;
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u32 size;
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};
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struct lima_sched_task {
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struct drm_sched_job base;
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struct lima_vm *vm;
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void *frame;
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struct xarray deps;
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unsigned long last_dep;
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struct lima_bo **bos;
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int num_bos;
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bool recoverable;
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struct lima_bo *heap;
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/* pipe fence */
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struct dma_fence *fence;
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};
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struct lima_sched_context {
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struct drm_sched_entity base;
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};
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#define LIMA_SCHED_PIPE_MAX_MMU 8
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#define LIMA_SCHED_PIPE_MAX_L2_CACHE 2
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#define LIMA_SCHED_PIPE_MAX_PROCESSOR 8
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struct lima_ip;
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struct lima_sched_pipe {
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struct drm_gpu_scheduler base;
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u64 fence_context;
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u32 fence_seqno;
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spinlock_t fence_lock;
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struct lima_device *ldev;
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struct lima_sched_task *current_task;
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struct lima_vm *current_vm;
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struct lima_ip *mmu[LIMA_SCHED_PIPE_MAX_MMU];
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int num_mmu;
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struct lima_ip *l2_cache[LIMA_SCHED_PIPE_MAX_L2_CACHE];
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int num_l2_cache;
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struct lima_ip *processor[LIMA_SCHED_PIPE_MAX_PROCESSOR];
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int num_processor;
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struct lima_ip *bcast_processor;
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struct lima_ip *bcast_mmu;
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u32 done;
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bool error;
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atomic_t task;
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int frame_size;
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struct kmem_cache *task_slab;
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int (*task_validate)(struct lima_sched_pipe *pipe, struct lima_sched_task *task);
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void (*task_run)(struct lima_sched_pipe *pipe, struct lima_sched_task *task);
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void (*task_fini)(struct lima_sched_pipe *pipe);
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void (*task_error)(struct lima_sched_pipe *pipe);
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void (*task_mmu_error)(struct lima_sched_pipe *pipe);
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int (*task_recover)(struct lima_sched_pipe *pipe);
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struct work_struct recover_work;
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};
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int lima_sched_task_init(struct lima_sched_task *task,
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struct lima_sched_context *context,
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struct lima_bo **bos, int num_bos,
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struct lima_vm *vm);
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void lima_sched_task_fini(struct lima_sched_task *task);
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int lima_sched_context_init(struct lima_sched_pipe *pipe,
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struct lima_sched_context *context,
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atomic_t *guilty);
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void lima_sched_context_fini(struct lima_sched_pipe *pipe,
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struct lima_sched_context *context);
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struct dma_fence *lima_sched_context_queue_task(struct lima_sched_context *context,
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struct lima_sched_task *task);
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int lima_sched_pipe_init(struct lima_sched_pipe *pipe, const char *name);
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void lima_sched_pipe_fini(struct lima_sched_pipe *pipe);
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void lima_sched_pipe_task_done(struct lima_sched_pipe *pipe);
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static inline void lima_sched_pipe_mmu_error(struct lima_sched_pipe *pipe)
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{
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pipe->error = true;
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pipe->task_mmu_error(pipe);
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}
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int lima_sched_slab_init(void);
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void lima_sched_slab_fini(void);
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#endif
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