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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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8d2511686e
Expose GPU PCIe average temperature and its limits via hwmon sysfs entry temp5_xxx. Update Xe hwmon sysfs documentation for this. v2: Update kernel version in Xe hwmon documentation. (Raag) v3: - Address review comments from Raag. - Remove redundant debug log. - Update kernel version in Xe hwmon documentation. (Raag) v4: - Address review comments from Raag. - Group new temperature attributes with existing temperature attributes as per channel index in Xe hwmon documentation. - Use TEMP_MASK instead of TEMP_MASK_MAILBOX. - Add PCIE_SENSOR_MASK which uses REG_FIELD_GET as replacement of PCIE_SENSOR_SHIFT. v5: - Address review comments from Raag. - Use REG_FIELD_GET to get PCIe temperature. - Move PCIE_SENSOR_GROUP_ID and PCIE_SENSOR_MASK to xe_pcode_api.h - Cosmetic change. Signed-off-by: Karthik Poosa <karthik.poosa@intel.com> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Link: https://patch.msgid.link/20260112203521.1014388-4-karthik.poosa@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
104 lines
3.4 KiB
C
104 lines
3.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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/* Internal to xe_pcode */
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#include "regs/xe_reg_defs.h"
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#define PCODE_MAILBOX XE_REG(0x138124)
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#define PCODE_READY REG_BIT(31)
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#define PCODE_MB_PARAM2 REG_GENMASK(23, 16)
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#define PCODE_MB_PARAM1 REG_GENMASK(15, 8)
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#define PCODE_MB_COMMAND REG_GENMASK(7, 0)
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#define PCODE_ERROR_MASK 0xFF
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#define PCODE_SUCCESS 0x0
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#define PCODE_ILLEGAL_CMD 0x1
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#define PCODE_TIMEOUT 0x2
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#define PCODE_ILLEGAL_DATA 0x3
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#define PCODE_ILLEGAL_SUBCOMMAND 0x4
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#define PCODE_LOCKED 0x6
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#define PCODE_GT_RATIO_OUT_OF_RANGE 0x10
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#define PCODE_REJECTED 0x11
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#define PCODE_DATA0 XE_REG(0x138128)
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#define PCODE_DATA1 XE_REG(0x13812C)
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/* Min Freq QOS Table */
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#define PCODE_WRITE_MIN_FREQ_TABLE 0x8
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#define PCODE_READ_MIN_FREQ_TABLE 0x9
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#define PCODE_FREQ_RING_RATIO_SHIFT 16
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/* PCODE Init */
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#define DGFX_PCODE_STATUS 0x7E
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#define DGFX_GET_INIT_STATUS 0x0
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#define DGFX_INIT_STATUS_COMPLETE 0x1
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#define DGFX_LINK_DOWNGRADE_STATUS REG_BIT(31)
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#define PCODE_POWER_SETUP 0x7C
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#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
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#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
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#define POWER_SETUP_I1_WATTS REG_BIT(31)
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#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
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#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
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#define READ_PSYSGPU_POWER_LIMIT 0x6
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#define WRITE_PSYSGPU_POWER_LIMIT 0x7
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#define READ_PACKAGE_POWER_LIMIT 0x8
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#define WRITE_PACKAGE_POWER_LIMIT 0x9
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#define READ_PL_FROM_FW 0x1
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#define READ_PL_FROM_PCODE 0x0
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#define PCODE_THERMAL_INFO 0x25
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#define READ_THERMAL_LIMITS 0x0
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#define READ_THERMAL_CONFIG 0x1
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#define READ_THERMAL_DATA 0x2
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#define PCIE_SENSOR_GROUP_ID 0x2
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#define PCIE_SENSOR_MASK REG_GENMASK(31, 16)
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#define PCODE_LATE_BINDING 0x5C
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#define GET_CAPABILITY_STATUS 0x0
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#define V1_FAN_SUPPORTED REG_BIT(0)
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#define VR_PARAMS_SUPPORTED REG_BIT(3)
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#define V1_FAN_PROVISIONED REG_BIT(16)
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#define VR_PARAMS_PROVISIONED REG_BIT(19)
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#define GET_VERSION_LOW 0x1
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#define GET_VERSION_HIGH 0x2
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#define MAJOR_VERSION_MASK REG_GENMASK(31, 16)
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#define MINOR_VERSION_MASK REG_GENMASK(15, 0)
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#define HOTFIX_VERSION_MASK REG_GENMASK(31, 16)
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#define BUILD_VERSION_MASK REG_GENMASK(15, 0)
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#define FAN_TABLE 1
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#define VR_CONFIG 2
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#define PCODE_FREQUENCY_CONFIG 0x6e
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/* Frequency Config Sub Commands (param1) */
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#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
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#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
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/* Domain IDs (param2) */
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#define PCODE_MBOX_DOMAIN_HBM 0x2
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#define FAN_SPEED_CONTROL 0x7D
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#define FSC_READ_NUM_FANS 0x4
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#define PCODE_SCRATCH(x) XE_REG(0x138320 + ((x) * 4))
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/* PCODE_SCRATCH0 */
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#define BREADCRUMB_VERSION REG_GENMASK(31, 29)
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#define AUXINFO_REG_OFFSET REG_GENMASK(17, 15)
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#define OVERFLOW_REG_OFFSET REG_GENMASK(14, 12)
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#define HISTORY_TRACKING REG_BIT(11)
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#define OVERFLOW_SUPPORT REG_BIT(10)
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#define AUXINFO_SUPPORT REG_BIT(9)
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#define FDO_MODE REG_BIT(4)
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#define BOOT_STATUS REG_GENMASK(3, 1)
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#define CRITICAL_FAILURE 4
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#define NON_CRITICAL_FAILURE 7
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/* Auxiliary info bits */
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#define AUXINFO_HISTORY_OFFSET REG_GENMASK(31, 29)
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#define BMG_PCIE_CAP XE_REG(0x138340)
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#define LINK_DOWNGRADE REG_GENMASK(1, 0)
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#define DOWNGRADE_CAPABLE 2
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