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8367585154
clangd reports many "unused header" warnings throughout the Xe driver. Start working to clean this up by removing unnecessary includes in our .c files and/or replacing them with explicit includes of other headers that were previously being included indirectly. By far the most common offender here was unnecessary inclusion of xe_gt.h. That likely originates from the early days of xe.ko when xe_mmio did not exist and all register accesses, including those unrelated to GTs, were done with GT functions. There's still a lot of additional #include cleanup that can be done in the headers themselves; that will come as a followup series. v2: - Squash the 79-patch series down to a single patch. (MattB) Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260115032803.4067824-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
85 lines
1.9 KiB
C
85 lines
1.9 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include <linux/math64.h>
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#include "xe_gt_clock.h"
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#include "regs/xe_gt_regs.h"
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#include "xe_gt_types.h"
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#include "xe_gt_printk.h"
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#include "xe_mmio.h"
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#define f19_2_mhz 19200000
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#define f24_mhz 24000000
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#define f25_mhz 25000000
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#define f38_4_mhz 38400000
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#define ts_base_83 83333
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#define ts_base_52 52083
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#define ts_base_80 80000
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static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
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u32 *timestamp_base)
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{
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u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,
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rpm_config_reg);
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switch (crystal_clock) {
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
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*freq = f24_mhz;
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*timestamp_base = ts_base_83;
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return;
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
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*freq = f19_2_mhz;
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*timestamp_base = ts_base_52;
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return;
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
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*freq = f38_4_mhz;
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*timestamp_base = ts_base_52;
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return;
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
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*freq = f25_mhz;
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*timestamp_base = ts_base_80;
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return;
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default:
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xe_gt_warn(gt, "Invalid crystal clock frequency: %u", crystal_clock);
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*freq = 0;
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*timestamp_base = 0;
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return;
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}
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}
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int xe_gt_clock_init(struct xe_gt *gt)
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{
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u32 freq;
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u32 c0;
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c0 = xe_mmio_read32(>->mmio, RPM_CONFIG0);
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read_crystal_clock(gt, c0, &freq, >->info.timestamp_base);
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/*
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* Now figure out how the command stream's timestamp
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* register increments from this frequency (it might
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* increment only every few clock cycle).
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*/
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freq >>= 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);
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gt->info.reference_clock = freq;
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return 0;
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}
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/**
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* xe_gt_clock_interval_to_ms - Convert sampled GT clock ticks to msec
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*
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* @gt: the &xe_gt
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* @count: count of GT clock ticks
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*
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* Returns: time in msec
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*/
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u64 xe_gt_clock_interval_to_ms(struct xe_gt *gt, u64 count)
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{
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return mul_u64_u32_div(count, MSEC_PER_SEC, gt->info.reference_clock);
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}
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