mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-03-22 07:27:12 +08:00
bf4afc53b7
This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
89 lines
2.0 KiB
C
89 lines
2.0 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright 2023, Intel Corporation.
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*/
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#include "intel_dsb_buffer.h"
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#include "xe_bo.h"
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#include "xe_device.h"
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#include "xe_device_types.h"
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struct intel_dsb_buffer {
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u32 *cmd_buf;
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struct xe_bo *bo;
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size_t buf_size;
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};
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u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
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{
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return xe_bo_ggtt_addr(dsb_buf->bo);
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}
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void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
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{
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iosys_map_wr(&dsb_buf->bo->vmap, idx * 4, u32, val);
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}
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u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
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{
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return iosys_map_rd(&dsb_buf->bo->vmap, idx * 4, u32);
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}
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void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
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{
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WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
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iosys_map_memset(&dsb_buf->bo->vmap, idx * 4, val, size);
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}
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struct intel_dsb_buffer *intel_dsb_buffer_create(struct drm_device *drm, size_t size)
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{
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struct xe_device *xe = to_xe_device(drm);
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struct intel_dsb_buffer *dsb_buf;
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struct xe_bo *obj;
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int ret;
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dsb_buf = kzalloc_obj(*dsb_buf);
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if (!dsb_buf)
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return ERR_PTR(-ENOMEM);
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/* Set scanout flag for WC mapping */
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obj = xe_bo_create_pin_map_novm(xe, xe_device_get_root_tile(xe),
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PAGE_ALIGN(size),
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ttm_bo_type_kernel,
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XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
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XE_BO_FLAG_SCANOUT | XE_BO_FLAG_GGTT, false);
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if (IS_ERR(obj)) {
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ret = PTR_ERR(obj);
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goto err_pin_map;
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}
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dsb_buf->bo = obj;
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dsb_buf->buf_size = size;
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return dsb_buf;
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err_pin_map:
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kfree(dsb_buf);
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return ERR_PTR(ret);
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}
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void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
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{
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xe_bo_unpin_map_no_vm(dsb_buf->bo);
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kfree(dsb_buf);
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}
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void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
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{
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struct xe_device *xe = dsb_buf->bo->tile->xe;
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/*
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* The memory barrier here is to ensure coherency of DSB vs MMIO,
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* both for weak ordering archs and discrete cards.
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*/
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xe_device_wmb(xe);
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xe_device_l2_flush(xe);
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}
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