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0672cf9828
Both sharpness and panel fitter use pipe scaler,
but only one can be enabled at a time. Furthermore
sharpness uses second scaler. So for CASF, check if
second scaler is available and make sure that only
either of panel fitter or sharpness is enabled at
a time.
v2: Add the panel fitting check before enabling sharpness
v3: Reframe commit message[Arun]
v4: Replace string based comparison with plane_state[Jani]
v5: Rebase
v6: Fix build issue
v7: Remove scaler id from verify_crtc_state[Ankit]
v8: Change the patch title. Add code comment.
Move the config part in patch#6. [Ankit]
v9: Refactor the patch[Ankit]
v10: Modify the header of patch[Ankit]
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251028120747.3027332-8-ankit.k.nautiyal@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
291 lines
8.2 KiB
C
291 lines
8.2 KiB
C
// SPDX-License-Identifier: MIT
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/* Copyright © 2025 Intel Corporation */
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#include <drm/drm_print.h>
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#include "i915_reg.h"
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#include "intel_casf.h"
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#include "intel_casf_regs.h"
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#include "intel_de.h"
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#include "intel_display_regs.h"
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#include "intel_display_types.h"
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#include "skl_scaler.h"
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#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
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#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
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#define FILTER_COEFF_0_125 125
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#define FILTER_COEFF_0_25 250
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#define FILTER_COEFF_0_5 500
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#define FILTER_COEFF_1_0 1000
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#define FILTER_COEFF_0_0 0
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#define SET_POSITIVE_SIGN(x) ((x) & (~SIGN))
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/**
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* DOC: Content Adaptive Sharpness Filter (CASF)
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*
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* Starting from LNL the display engine supports an
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* adaptive sharpening filter, enhancing the image
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* quality. The display hardware utilizes the second
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* pipe scaler for implementing CASF.
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* If sharpness is being enabled then pipe scaling
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* cannot be used.
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* This filter operates on a region of pixels based
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* on the tap size. Coefficients are used to generate
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* an alpha value which blends the sharpened image to
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* original image.
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*/
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/* Default LUT values to be loaded one time. */
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static const u16 sharpness_lut[] = {
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4095, 2047, 1364, 1022, 816, 678, 579,
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504, 444, 397, 357, 323, 293, 268, 244, 224,
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204, 187, 170, 154, 139, 125, 111, 98, 85,
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73, 60, 48, 36, 24, 12, 0
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};
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const u16 filtercoeff_1[] = {
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FILTER_COEFF_0_0, FILTER_COEFF_0_0, FILTER_COEFF_0_5,
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FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0,
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FILTER_COEFF_0_0,
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};
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const u16 filtercoeff_2[] = {
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FILTER_COEFF_0_0, FILTER_COEFF_0_25, FILTER_COEFF_0_5,
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FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25,
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FILTER_COEFF_0_0,
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};
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const u16 filtercoeff_3[] = {
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FILTER_COEFF_0_125, FILTER_COEFF_0_25, FILTER_COEFF_0_5,
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FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25,
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FILTER_COEFF_0_125,
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};
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static void intel_casf_filter_lut_load(struct intel_crtc *crtc,
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const struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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int i;
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intel_de_write(display, SHRPLUT_INDEX(crtc->pipe),
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INDEX_AUTO_INCR | INDEX_VALUE(0));
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for (i = 0; i < ARRAY_SIZE(sharpness_lut); i++)
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intel_de_write(display, SHRPLUT_DATA(crtc->pipe),
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sharpness_lut[i]);
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}
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void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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int win_size;
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intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK,
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FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
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win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1));
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intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, 1), win_size);
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}
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static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
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{
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const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
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u32 total_pixels = mode->hdisplay * mode->vdisplay;
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if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
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crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
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else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
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crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
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else
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crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
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}
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int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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if (!HAS_CASF(display))
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return 0;
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if (crtc_state->uapi.sharpness_strength == 0) {
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crtc_state->hw.casf_params.casf_enable = false;
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crtc_state->hw.casf_params.strength = 0;
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return 0;
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}
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crtc_state->hw.casf_params.casf_enable = true;
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/*
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* HW takes a value in form (1.0 + strength) in 4.4 fixed format.
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* Strength is from 0.0-14.9375 ie from 0-239.
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* User can give value from 0-255 but is clamped to 239.
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* Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
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* 6.3125 in 4.4 format is b01100101 which is equal to 101.
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* Also 85 + 16 = 101.
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*/
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crtc_state->hw.casf_params.strength =
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min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
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intel_casf_compute_win_size(crtc_state);
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intel_casf_scaler_compute_config(crtc_state);
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return 0;
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}
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void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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u32 sharp;
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sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
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if (sharp & FILTER_EN) {
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if (drm_WARN_ON(display->drm,
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REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
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crtc_state->hw.casf_params.strength = 0;
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else
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crtc_state->hw.casf_params.strength =
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REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
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crtc_state->hw.casf_params.casf_enable = true;
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crtc_state->hw.casf_params.win_size =
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REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
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}
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}
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bool intel_casf_needs_scaler(const struct intel_crtc_state *crtc_state)
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{
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if (crtc_state->hw.casf_params.casf_enable)
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return true;
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return false;
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}
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static int casf_coeff_tap(int i)
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{
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return i % SCALER_FILTER_NUM_TAPS;
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}
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static u32 casf_coeff(struct intel_crtc_state *crtc_state, int t)
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{
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struct scaler_filter_coeff value;
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u32 coeff;
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value = crtc_state->hw.casf_params.coeff[t];
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value.sign = 0;
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coeff = value.sign << 15 | value.exp << 12 | value.mantissa << 3;
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return coeff;
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}
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/*
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* 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
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* To enable casf: program scaler coefficients with the coeffients
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* that are calculated and stored in hw.casf_params.coeff as per
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* SCALER_COEFFICIENT_FORMAT
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*/
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static void intel_casf_write_coeff(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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int id = crtc_state->scaler_state.scaler_id;
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int i;
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if (id != 1) {
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drm_WARN(display->drm, 0, "Second scaler not enabled\n");
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return;
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}
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intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0),
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PS_COEF_INDEX_AUTO_INC);
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for (i = 0; i < 17 * SCALER_FILTER_NUM_TAPS; i += 2) {
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u32 tmp;
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int t;
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t = casf_coeff_tap(i);
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tmp = casf_coeff(crtc_state, t);
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t = casf_coeff_tap(i + 1);
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tmp |= casf_coeff(crtc_state, t) << 16;
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intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0),
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tmp);
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}
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}
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static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff,
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u16 coefficient)
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{
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if (coefficient < 25) {
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coeff->mantissa = (coefficient * 2048) / 100;
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coeff->exp = 3;
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} else if (coefficient < 50) {
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coeff->mantissa = (coefficient * 1024) / 100;
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coeff->exp = 2;
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} else if (coefficient < 100) {
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coeff->mantissa = (coefficient * 512) / 100;
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coeff->exp = 1;
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} else {
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coeff->mantissa = (coefficient * 256) / 100;
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coeff->exp = 0;
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}
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}
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void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state)
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{
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const u16 *filtercoeff;
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u16 filter_coeff[SCALER_FILTER_NUM_TAPS];
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u16 sumcoeff = 0;
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int i;
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if (crtc_state->hw.casf_params.win_size == 0)
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filtercoeff = filtercoeff_1;
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else if (crtc_state->hw.casf_params.win_size == 1)
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filtercoeff = filtercoeff_2;
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else
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filtercoeff = filtercoeff_3;
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for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++)
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sumcoeff += *(filtercoeff + i);
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for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) {
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filter_coeff[i] = (*(filtercoeff + i) * 100 / sumcoeff);
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convert_sharpness_coef_binary(&crtc_state->hw.casf_params.coeff[i],
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filter_coeff[i]);
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}
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}
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void intel_casf_enable(struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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u32 sharpness_ctl;
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intel_casf_filter_lut_load(crtc, crtc_state);
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intel_casf_write_coeff(crtc_state);
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sharpness_ctl = FILTER_EN | FILTER_STRENGTH(crtc_state->hw.casf_params.strength);
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sharpness_ctl |= crtc_state->hw.casf_params.win_size;
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intel_de_write(display, SHARPNESS_CTL(crtc->pipe), sharpness_ctl);
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skl_scaler_setup_casf(crtc_state);
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}
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void intel_casf_disable(const struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(crtc_state);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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intel_de_write(display, SKL_PS_CTRL(crtc->pipe, 1), 0);
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intel_de_write(display, SKL_PS_WIN_POS(crtc->pipe, 1), 0);
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intel_de_write(display, SHARPNESS_CTL(crtc->pipe), 0);
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intel_de_write(display, SKL_PS_WIN_SZ(crtc->pipe, 1), 0);
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}
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