Yihan Zhu 02a940da2c drm/amd/display: handle max_downscale_src_width fail check ... [WHY] If max_downscale_src_width check fails, we exit early from TAP calculation and left a NULL value to the scaling data structure to cause the zero divide in the DML validation. [HOW] Call set default TAP calculation before early exit in get_optimal_number_of_taps due to max downscale limit exceed. Reviewed-by: Samson Tam <samson.tam@amd.com> Signed-off-by: Yihan Zhu <Yihan.Zhu@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2025-02-25 11:45:11 -05:00
..
dcn10	drm/amd/display: Optimize cursor position updates	2025-01-24 09:56:28 -05:00
dcn20	drm/amd/display: Move SPL to a new path	2025-02-12 21:03:01 -05:00
dcn30	drm/amd/display: handle max_downscale_src_width fail check	2025-02-25 11:45:11 -05:00
dcn32	drm/amd/display: Move SPL to a new path	2025-02-12 21:03:01 -05:00
dcn35	drm/amd/display: w/a to program DISPCLK_R_GATE_DISABLE DCN35	2024-10-22 17:50:38 -04:00
dcn201	drm/amd/display: Remove unnecessary files	2024-04-30 09:52:21 -04:00
dcn401	drm/amd/display: Refactor DCN4x and related code	2025-02-25 11:44:02 -05:00
Makefile	drm/amd/display: Add misc DC changes for DCN401	2024-04-26 17:23:34 -04:00